| Message ID | tencent_195F1119DC8F547C905D5ED127D173EFAE08@qq.com |
|---|---|
| State | New |
| Headers | show |
| Series | [V5] phy: freescale: fsl-samsung-hdmi: fix build error in fsl_samsung_hdmi_phy_configure_pll_lock_det | expand |
On Mon, Jan 13, 2025 at 2:41 AM <xiaopeitux@foxmail.com> wrote: > > From: Pei Xiao <xiaopei01@kylinos.cn> > > FIELD_PREP() checks that a value fits into the available bitfield, > but the index div equals to 4,is out of range. > > which gcc complains about: > In function ‘fsl_samsung_hdmi_phy_configure_pll_lock_det’, > inlined from ‘fsl_samsung_hdmi_phy_configure’ at > drivers/phy/freescale/phy-fsl-samsung-hdmi.c :470:2: > ././include/linux/compiler_types.h:542:38: error: call to ‘__compiletime_assert_538’ > declared with attribute error: FIELD_PREP: value too large for the field > 542 | _compiletime_assert(condition, msg, __compiletime_assert_, > __COUNTER__) > | ^ > ././include/linux/compiler_types.h:523:4: note: in definition of > macro ‘__compiletime_assert’ 523 | prefix ## suffix(); > | ^~~~~~ > ././include/linux/compiler_types.h:542:2: note: in expansion of macro > ‘_compiletime_assert’ > 542 | _compiletime_assert(condition, msg, __compiletime_assert_, > __COUNTER__) > > REG12_CK_DIV_MASK only two bit, limit div to range 0~3, > so build error will fix. > LGTM. Reviewed-by: Adam Ford <aford173@gmail.com> > Fixes: d567679f2b6a ("phy: freescale: fsl-samsung-hdmi: Clean up fld_tg_code calculation") > Signed-off-by: Pei Xiao <xiaopei01@kylinos.cn> > > Changlog: > --- > V5: add return ret from Geert suggestion > V4: change to use if statement > V3: change to use do-while > V2: change to use logical AND > --- > drivers/phy/freescale/phy-fsl-samsung-hdmi.c | 13 +++++++++++-- > 1 file changed, 11 insertions(+), 2 deletions(-) > > diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c > index 5eac70a1e858..6817ceabaab4 100644 > --- a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c > +++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c > @@ -325,7 +325,7 @@ to_fsl_samsung_hdmi_phy(struct clk_hw *hw) > return container_of(hw, struct fsl_samsung_hdmi_phy, hw); > } > > -static void > +static int > fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_samsung_hdmi_phy *phy, > const struct phy_config *cfg) > { > @@ -341,6 +341,9 @@ fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_samsung_hdmi_phy *phy, > break; > } > > + if (unlikely(div == 4)) > + return -EINVAL; > + > writeb(FIELD_PREP(REG12_CK_DIV_MASK, div), phy->regs + PHY_REG(12)); > > /* > @@ -364,6 +367,8 @@ fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_samsung_hdmi_phy *phy, > FIELD_PREP(REG14_RP_CODE_MASK, 2) | > FIELD_PREP(REG14_TG_CODE_HIGH_MASK, fld_tg_code >> 8), > phy->regs + PHY_REG(14)); > + > + return 0; > } > > static unsigned long fsl_samsung_hdmi_phy_find_pms(unsigned long fout, u8 *p, u16 *m, u8 *s) > @@ -467,7 +472,11 @@ static int fsl_samsung_hdmi_phy_configure(struct fsl_samsung_hdmi_phy *phy, > writeb(REG21_SEL_TX_CK_INV | FIELD_PREP(REG21_PMS_S_MASK, > cfg->pll_div_regs[2] >> 4), phy->regs + PHY_REG(21)); > > - fsl_samsung_hdmi_phy_configure_pll_lock_det(phy, cfg); > + ret = fsl_samsung_hdmi_phy_configure_pll_lock_det(phy, cfg); > + if (ret) { > + dev_err(phy->dev, "pixclock too large\n"); > + return ret; > + } > > writeb(REG33_FIX_DA | REG33_MODE_SET_DONE, phy->regs + PHY_REG(33)); > > -- > 2.25.1 >
diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c index 5eac70a1e858..6817ceabaab4 100644 --- a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c +++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c @@ -325,7 +325,7 @@ to_fsl_samsung_hdmi_phy(struct clk_hw *hw) return container_of(hw, struct fsl_samsung_hdmi_phy, hw); } -static void +static int fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_samsung_hdmi_phy *phy, const struct phy_config *cfg) { @@ -341,6 +341,9 @@ fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_samsung_hdmi_phy *phy, break; } + if (unlikely(div == 4)) + return -EINVAL; + writeb(FIELD_PREP(REG12_CK_DIV_MASK, div), phy->regs + PHY_REG(12)); /* @@ -364,6 +367,8 @@ fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_samsung_hdmi_phy *phy, FIELD_PREP(REG14_RP_CODE_MASK, 2) | FIELD_PREP(REG14_TG_CODE_HIGH_MASK, fld_tg_code >> 8), phy->regs + PHY_REG(14)); + + return 0; } static unsigned long fsl_samsung_hdmi_phy_find_pms(unsigned long fout, u8 *p, u16 *m, u8 *s) @@ -467,7 +472,11 @@ static int fsl_samsung_hdmi_phy_configure(struct fsl_samsung_hdmi_phy *phy, writeb(REG21_SEL_TX_CK_INV | FIELD_PREP(REG21_PMS_S_MASK, cfg->pll_div_regs[2] >> 4), phy->regs + PHY_REG(21)); - fsl_samsung_hdmi_phy_configure_pll_lock_det(phy, cfg); + ret = fsl_samsung_hdmi_phy_configure_pll_lock_det(phy, cfg); + if (ret) { + dev_err(phy->dev, "pixclock too large\n"); + return ret; + } writeb(REG33_FIX_DA | REG33_MODE_SET_DONE, phy->regs + PHY_REG(33));