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Fri, 1 Feb 2019 16:47:16 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, Lukasz Luba Subject: [PATCH v4 0/8] Exynos5 Dynamic Memory Controller driver Date: Fri, 1 Feb 2019 17:46:44 +0100 Message-Id: <1549039612-28905-1-git-send-email-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.7.4 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFmplleLIzCtJLcpLzFFi42LZduzneV3RipAYg63TDCw2zljPanH9y3NW i/lHzrFa9D9+zWxx/vwGdouzTW/YLW41yFhc3jWHzeJz7xFGixnn9zFZrD1yl93iduMKNovD b9pZHXg9Nq3qZPM4+G4Pk0ffllWMHp83yQWwRHHZpKTmZJalFunbJXBlHLvSy1rwTaTiwMOZ bA2Mr/m7GDk5JARMJCY132TvYuTiEBJYwShx4eFqRgjnC6PE9g8PmSCcz4wSyxedYoFp6Tgx iQUisZxRYsbWdna4luXdE9m6GDk42AT0JHasKgRpEBGolrhzfT8zSA2zwFtGiZk3v4BNEhZw kNi47BATiM0ioCpxY8UBZhCbV8BLYufFaewQ2+Qkbp7rBGuWEPjNJrFvzVSohIvE5UPn2SBs YYlXx7dAxWUkTk/ugTq1WOJsxyqomhqJ9pM7oGqsJQ4fv8gKciizgKbE+l36EGFHiaZDrSwg YQkBPokbbwVBwsxA5qRt05khwrwSHW1CENUaElt6LjBB2GISy9fAXOwh8X3zXbDhQgKxEk3L UiYwys1CWLWAkXEVo3hqaXFuemqxYV5quV5xYm5xaV66XnJ+7iZGYOI4/e/4px2MXy8lHWIU 4GBU4uHd8CsoRog1say4MvcQowQHs5IIr1NWSIwQb0piZVVqUX58UWlOavEhRmkOFiVx3mqG B9FCAumJJanZqakFqUUwWSYOTqkGxvUPtHhb2Dvq1HtCe21cbF/Ir72rvev43hrWsMt51z+L WzB8UE+e6i/M+t+w9KzhbcEd+/S/zlhmUbj4J9PONXPurYqpkNnj/KqE59StF28ulkx98HdR 3xLnkrbIJi6fa1UsN2Ru/5A3tNm6u9jjy9xkre6PSWLNc/6/lBEWDE3jfzlBeFKujhJLcUai oRZzUXEiANawIV4YAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrLLMWRmVeSWpSXmKPExsVy+t/xe7qiFSExBrP3MllsnLGe1eL6l+es FvOPnGO16H/8mtni/PkN7BZnm96wW9xqkLG4vGsOm8Xn3iOMFjPO72OyWHvkLrvF7cYVbBaH 37SzOvB6bFrVyeZx8N0eJo++LasYPT5vkgtgidKzKcovLUlVyMgvLrFVija0MNIztLTQMzKx 1DM0No+1MjJV0rezSUnNySxLLdK3S9DLOHall7Xgm0jFgYcz2RoYX/N3MXJySAiYSHScmMTS xcjFISSwlFGi9eVONoiEmMSkfdvZIWxhiT/Xutggij4xStw8v4W5i5GDg01AT2LHqkKQGhGB eon+N5fAapgFvjNKHHoygREkISzgILFx2SEmEJtFQFXixooDzCA2r4CXxM6L06AWyEncPNfJ PIGRZwEjwypGkdTS4tz03GJDveLE3OLSvHS95PzcTYzAoN127OfmHYyXNgYfYhTgYFTi4d3w KyhGiDWxrLgy9xCjBAezkgivU1ZIjBBvSmJlVWpRfnxRaU5q8SFGU6DlE5mlRJPzgRGVVxJv aGpobmFpaG5sbmxmoSTOe96gMkpIID2xJDU7NbUgtQimj4mDU6qBsYTFNufvgeshNnUKjCeL zd8odceoWuZW3GrNWXDzbPn6doUvrU7mv4Qqrjrtvnr7zr8rMdNT1kwNbyjldHvowyJhVs5l nVcpdSfDzWBmgMdelxWlt5mMIwsURd0jlsnseXDsR0Xz7I/hNbIB1a0GsZ5XEncdfaR37zZz tuPVGMu5x9YlucYqsRRnJBpqMRcVJwIAJmBc0HACAAA= X-CMS-MailID: 20190201164717eucas1p2ddf83cd5b7a5f53fdb866eeb8e991c71 X-Msg-Generator: CA X-RootMTR: 20190201164717eucas1p2ddf83cd5b7a5f53fdb866eeb8e991c71 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190201164717eucas1p2ddf83cd5b7a5f53fdb866eeb8e991c71 References: Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Hi all, This is v4 of the patch set which adds support of Dynamic Memory Controller for Exynos5422 SoC. The driver supports Dynamic Voltage and Frequency Scalling for the DMC and DRAM. It also provides needed timings for different speed operations of the DRAM memory. The patch set is based on tag: v5.0-rc4 changes: v4: - removed unneeded DPLL and G3D clocks IDs - changed names of parent clocks for mout_mx_mspll_ccore_phy_p and added one more parent: mout_sclk_epll - removed 933Mhz and 138MHz from the BPLL ratio table v3: - in DTS align to proper indent the clocks and clock-names entries v2: - changed file name exynos5-dmc.c -> exynos5422-dmc.c and related entries in other files - changed dt-binding file name - changed config entry to CONFIG_ARM_EXYNOS5422_DMC_DEVFREQ - removed sysfs and print info messages (print only one line) - removed function exynos5_read_chip_info and compact code - changed dt-binding patch and move it up in the patch set - new entries in MAINTAINERS are added with the driver c code - clean-up in DTS file: renamed nodes to 'ppmu' and 'memory-controller', entries moved to suggested location (before nocp nodes or after), moved according to alfabetical order, compacted clocks names with right indent. Regards, Lukasz Luba Lukasz Luba (8): clk: samsung: add needed IDs for DMC clocks in Exynos5420 clk: samsung: add new clocks for DMC for Exynos5422 SoC clk: samsung: add BPLL rate table for Exynos 5422 SoC drivers: devfreq: add DMC driver for Exynos5422 dt-bindings: devfreq: add Exynos5422 DMC device description DT: arm: exynos: add DMC device for exynos5422 drivers: devfreq: events: add Exynos PPMU new events ARM: exynos_defconfig: enable DMC driver .../devicetree/bindings/devfreq/exynos5422-dmc.txt | 106 ++ MAINTAINERS | 8 + arch/arm/boot/dts/exynos5420.dtsi | 78 ++ arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 22 + arch/arm/configs/exynos_defconfig | 1 + drivers/clk/samsung/clk-exynos5420.c | 59 +- drivers/devfreq/Kconfig | 13 + drivers/devfreq/Makefile | 1 + drivers/devfreq/event/exynos-ppmu.c | 6 + drivers/devfreq/exynos5422-dmc.c | 1274 ++++++++++++++++++++ include/dt-bindings/clock/exynos5420.h | 16 +- 11 files changed, 1578 insertions(+), 6 deletions(-) create mode 100644 Documentation/devicetree/bindings/devfreq/exynos5422-dmc.txt create mode 100644 drivers/devfreq/exynos5422-dmc.c