From patchwork Fri Jul 2 03:12:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Lu X-Patchwork-Id: 12355405 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.9 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,UNPARSEABLE_RELAY,UNWANTED_LANGUAGE_BODY,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E34F0C11F6F for ; Fri, 2 Jul 2021 03:12:38 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CDB7261407 for ; Fri, 2 Jul 2021 03:12:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234769AbhGBDPI (ORCPT ); Thu, 1 Jul 2021 23:15:08 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:43094 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S234820AbhGBDPG (ORCPT ); Thu, 1 Jul 2021 23:15:06 -0400 X-UUID: b74212b83f8d44dc90ea041510caad80-20210702 X-UUID: b74212b83f8d44dc90ea041510caad80-20210702 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1533488050; Fri, 02 Jul 2021 11:12:17 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 2 Jul 2021 11:12:15 +0800 Received: from mtksdaap41.mediatek.inc (172.21.77.4) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 2 Jul 2021 11:12:15 +0800 From: Roger Lu To: Matthias Brugger , Enric Balletbo Serra , Kevin Hilman , Rob Herring , Nicolas Boichat , Stephen Boyd , Philipp Zabel CC: Fan Chen , HenryC Chen , YT Lee , Xiaoqing Liu , Charles Yang , Angus Lin , Mark Rutland , Nishanth Menon , Roger Lu , , , , , , , Guenter Roeck Subject: [PATCH v19 0/7] soc: mediatek: SVS: introduce MTK SVS Date: Fri, 2 Jul 2021 11:12:07 +0800 Message-ID: <20210702031214.21597-1-roger.lu@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org 1. SVS driver uses OPP adjust event in [1] to update OPP table voltage part. 2. SVS driver gets thermal/GPU device by node [2][3] and CPU device by get_cpu_device(). After retrieving subsys device, SVS driver calls device_link_add() to make sure probe/suspend callback priority. 3. SVS dts refers to reset controller [4] to help reset SVS HW. #mt8183 SVS related patches [1] https://patchwork.kernel.org/patch/11193513/ [2] https://patchwork.kernel.org/project/linux-mediatek/patch/20201013102358.22588-2-michael.kao@mediatek.com/ [3] https://patchwork.kernel.org/project/linux-mediatek/patch/20200306041345.259332-3-drinkcat@chromium.org/ #mt8192 SVS related patches [1] https://patchwork.kernel.org/patch/11193513/ [2] https://patchwork.kernel.org/project/linux-mediatek/patch/20201223074944.2061-1-michael.kao@mediatek.com/ [3] https://lore.kernel.org/patchwork/patch/1360551/ [4] https://patchwork.kernel.org/project/linux-mediatek/patch/20200817030324.5690-5-crystal.guo@mediatek.com/ changes since v18: - Add edge case handling in svs_set_freqs_pct_v3() when turn_pt is 0. If we don't add this handling, SVS HIGH bank will fill FREQPCT74 / FREQPCT30 with 0 and SVS controller won't run normally. - Remove redundant SVSB_MON_VOLT_IGNORE flag from svs_mt8192_banks[]'s low bank configuration. Roger Lu (7): [v19,1/7] dt-bindings: soc: mediatek: add mtk svs dt-bindings [v19,2/7] arm64: dts: mt8183: add svs device information [v19,3/7] soc: mediatek: SVS: introduce MTK SVS engine [v19,4/7] soc: mediatek: SVS: add debug commands [v19,5/7] dt-bindings: soc: mediatek: add mt8192 svs dt-bindings [v19,6/7] arm64: dts: mt8192: add svs device information [v19,7/7] soc: mediatek: SVS: add mt8192 SVS GPU driver .../bindings/soc/mediatek/mtk-svs.yaml | 92 + arch/arm64/boot/dts/mediatek/mt8183.dtsi | 15 + arch/arm64/boot/dts/mediatek/mt8192.dtsi | 34 + drivers/soc/mediatek/Kconfig | 10 + drivers/soc/mediatek/Makefile | 1 + drivers/soc/mediatek/mtk-svs.c | 2527 +++++++++++++++++ 6 files changed, 2679 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mtk-svs.yaml create mode 100644 drivers/soc/mediatek/mtk-svs.c