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Thu, 7 Jul 2022 16:50:20 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT003.mail.protection.outlook.com (10.13.173.162) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5417.15 via Frontend Transport; Thu, 7 Jul 2022 16:50:20 +0000 Received: from pyuan-desktop.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Thu, 7 Jul 2022 11:50:16 -0500 From: Perry Yuan To: , , CC: , , , , , , , , , , Perry Yuan Subject: [PATCH 00/12] AMD Pstate Enhancement And Issue Fixs Date: Thu, 7 Jul 2022 12:49:44 -0400 Message-ID: <20220707164944.210616-1-Perry.Yuan@amd.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 8c64e86b-5550-4c81-af21-08da6038c766 X-MS-TrafficTypeDiagnostic: CY4PR12MB1735:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jul 2022 16:50:20.5239 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8c64e86b-5550-4c81-af21-08da6038c766 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT003.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1735 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org This patchset adds support for precision boost hardware control for AMD processors. Meanwhile the patchset fixs lowest perf query and desired perf scope issues. Update transition delay and latency default value to meet SMU firmware requirement. and do some code cleanups, It also exports cpufreq cpu release and acquire for coming amd-pstate epp mode driver The patch series are tested on the AMD mobile and EYPC server systems. Perry Yuan (12): x86/msr: Add the MSR definition for AMD CPPC hardware control. cpufreq: amd-pstate: enable AMD Precision Boost mode switch cpufreq: amd-pstate: cleanup the unused and duplicated headers declaration cpufreq: amd-pstate: prefetch cppc_req_cached value in amd_pstate_cpu_init() cpufreq: amd-pstate: simplify cpudata pointer assignment cpufreq: amd_pstate: fix wrong lowest perf fetch cpufreq: amd_pstate: map desired perf into pstate scope for powersave governor cpufreq: amd-pstate: fix white-space cpufreq: amd-pstate: update pstate frequency transition delay time cpufreq: cpufreq: export cpufreq cpu release and acquire cpufreq: amd-pstate: add ACPI disabled check cpufreq: amd_pstate: update transition delay time to 1ms arch/x86/include/asm/msr-index.h | 3 ++ drivers/acpi/cppc_acpi.c | 3 ++ drivers/cpufreq/amd-pstate.c | 57 +++++++++++++++++++------------- drivers/cpufreq/cpufreq.c | 2 ++ 4 files changed, 42 insertions(+), 23 deletions(-)