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[83.9.29.16]) by smtp.gmail.com with ESMTPSA id o24-20020a056512051800b004a2c447598fsm2182944lfb.159.2023.03.07.17.27.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Mar 2023 17:27:15 -0800 (PST) From: Konrad Dybcio Subject: [PATCH 0/8] qcom-cpufreq-hw binding improvements Date: Wed, 08 Mar 2023 02:26:57 +0100 Message-Id: <20230308-topic-cpufreq_bindings-v1-0-3368473ec52d@linaro.org> MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAGHkB2QC/x2N0QrCMAwAf2Xk2UBdmU5/RUTaLt0CI6uNk8HYv xt8vIPjdlCqTAr3ZodKX1ZexOB8aiBNQUZCHoyhda133vX4WQonTGXNld6vyDKwjIpdvvbkQ75 dogeLY1DCWIOkyXJZ59lkqZR5+98ez+P4AXvYZLZ9AAAA To: "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Krzysztof Kozlowski , Manivannan Sadhasivam , Andy Gross , Bjorn Andersson Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1678238834; l=1470; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=xI1zlOQmpQoj7NqQfsUAGQS5w5X6WW+TqN5bUGAVdZY=; b=KxPHiETKTjI7JvF17ebvbBEqnysNlVPhuiU5/ZPy9YqTyLKrLtTimseEW+3EgQJVTkWkzL2/kHRh eXcQejQyDxudWrEVbEFwRqbb6v1h4Em4I5Njl0fnmEezETDLXh2j X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org This series tries to better sanitize what's actually allowed on which SoC and lowers the minimum frequency domain count to 1, as that's what's present on at least QCM2290. Signed-off-by: Konrad Dybcio --- Konrad Dybcio (8): dt-bindings: cpufreq: cpufreq-qcom-hw: Allow just 1 frequency domain dt-bindings: cpufreq: cpufreq-qcom-hw: Sanitize data per compatible dt-bindings: cpufreq: cpufreq-qcom-hw: Add QCM2290 arm64: dts: qcom: sc7180: Add SoC-specific compatible to cpufreq_hw arm64: dts: qcom: sdm845: Add SoC-specific compatible to cpufreq_hw arm64: dts: qcom: sm6115: Add SoC-specific compatible to cpufreq_hw arm64: dts: qcom: sm6350: Add SoC-specific compatible to cpufreq_hw arm64: dts: qcom: sm8150: Add SoC-specific compatible to cpufreq_hw .../bindings/cpufreq/cpufreq-qcom-hw.yaml | 118 ++++++++++++++++++++- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm6115.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +- 6 files changed, 120 insertions(+), 8 deletions(-) --- base-commit: 709c6adf19dc558e44ab5c01659b09a16a2d3c82 change-id: 20230308-topic-cpufreq_bindings-5f78e3af96b3 Best regards,