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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SN1PEPF000397B2.mail.protection.outlook.com (10.167.248.56) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7762.17 via Frontend Transport; Thu, 11 Jul 2024 10:25:28 +0000 Received: from shatadru.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 11 Jul 2024 05:25:20 -0500 From: Dhananjay Ugwekar To: , , , , , , , , , , , , , , , , , CC: , , , , , , , , , Subject: [PATCH v4 00/11] Add per-core RAPL energy counter support for AMD CPUs Date: Thu, 11 Jul 2024 10:24:26 +0000 Message-ID: <20240711102436.4432-1-Dhananjay.Ugwekar@amd.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397B2:EE_|CY5PR12MB6082:EE_ X-MS-Office365-Filtering-Correlation-Id: 41228f73-c5fd-4ff5-3011-08dca193c965 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|1800799024|82310400026|36860700013|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jul 2024 10:25:28.8540 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 41228f73-c5fd-4ff5-3011-08dca193c965 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6082 Currently the energy-cores event in the power PMU aggregates energy consumption data at a package level. On the other hand the core energy RAPL counter in AMD CPUs has a core scope (which means the energy consumption is recorded separately for each core). Earlier efforts to add the core event in the power PMU had failed [1], due to the difference in the scope of these two events. Hence, there is a need for a new core scope PMU. This patchset adds a new "power_per_core" PMU alongside the existing "power" PMU, which will be responsible for collecting the new "energy-per-core" event. Tested the package level and core level PMU counters with workloads pinned to different CPUs. Results with workload pinned to CPU 1 in Core 1 on an AMD Zen4 Genoa machine: $ perf stat -a --per-core -e power_per_core/energy-per-core/ -- sleep 1 Performance counter stats for 'system wide': S0-D0-C0 1 0.02 Joules power_per_core/energy-per-core/ S0-D0-C1 1 5.72 Joules power_per_core/energy-per-core/ S0-D0-C2 1 0.02 Joules power_per_core/energy-per-core/ S0-D0-C3 1 0.02 Joules power_per_core/energy-per-core/ S0-D0-C4 1 0.02 Joules power_per_core/energy-per-core/ S0-D0-C5 1 0.02 Joules power_per_core/energy-per-core/ S0-D0-C6 1 0.02 Joules power_per_core/energy-per-core/ S0-D0-C7 1 0.02 Joules power_per_core/energy-per-core/ S0-D0-C8 1 0.02 Joules power_per_core/energy-per-core/ S0-D0-C9 1 0.02 Joules power_per_core/energy-per-core/ S0-D0-C10 1 0.02 Joules power_per_core/energy-per-core/ [1]: https://lore.kernel.org/lkml/3e766f0e-37d4-0f82-3868-31b14228868d@linux.intel.com/ This patchset applies cleanly on top of v6.10-rc7 as well as latest tip/master. v4 changes: * Add patch 11 which removes the unused function cpu_to_rapl_pmu() * Add Rui's rb tag for patch 1 * Invert the pmu scope check logic in patch 2 (Peter) * Add comments explaining the scope check in patch 2 (Peter) * Use cpumask_var_t instead of cpumask_t in patch 5 (Peter) * Move renaming code to patch 8 (Rui) * Reorder the cleanup order of per-core and per-pkg PMU in patch 10 (Rui) * Add rapl_core_hw_unit variable to store the per-core PMU unit in patch 10 (Rui) PS: Scope check logic is still kept the same (i.e., all Intel systems being considered as die scope), Rui will be modifying it to limit the die-scope only to Cascadelake-AP in a future patch on top of this patchset. v3 changes: * Patch 1 added to introduce the logical_core_id which is unique across the system (Prateek) * Use the unique topology_logical_core_id() instead of topology_core_id() (which is only unique within a package on tested AMD and Intel systems) in Patch 10 v2 changes: * Patches 6,7,8 added to split some changes out of the last patch * Use container_of to get the rapl_pmus from event variable (Rui) * Set PERF_EV_CAP_READ_ACTIVE_PKG flag only for pkg scope PMU (Rui) * Use event id 0x1 for energy-per-core event (Rui) * Use PERF_RAPL_PER_CORE bit instead of adding a new flag to check for per-core counter hw support (Rui) Dhananjay Ugwekar (10): perf/x86/rapl: Fix the energy-pkg event for AMD CPUs perf/x86/rapl: Rename rapl_pmu variables perf/x86/rapl: Make rapl_model struct global perf/x86/rapl: Move cpumask variable to rapl_pmus struct perf/x86/rapl: Add wrapper for online/offline functions perf/x86/rapl: Add an argument to the cleanup and init functions perf/x86/rapl: Modify the generic variable names to *_pkg* perf/x86/rapl: Remove the global variable rapl_msrs perf/x86/rapl: Add per-core energy counter support for AMD CPUs perf/x86/rapl: Remove the unused function cpu_to_rapl_pmu K Prateek Nayak (1): x86/topology: Introduce topology_logical_core_id() Documentation/arch/x86/topology.rst | 4 + arch/x86/events/rapl.c | 454 ++++++++++++++++++-------- arch/x86/include/asm/processor.h | 1 + arch/x86/include/asm/topology.h | 1 + arch/x86/kernel/cpu/debugfs.c | 1 + arch/x86/kernel/cpu/topology_common.c | 1 + 6 files changed, 328 insertions(+), 134 deletions(-)