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([59.188.211.160]) by smtp.googlemail.com with ESMTPSA id d9443c01a7336-218a1dcb3ffsm79202565ad.75.2024.12.18.10.28.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Dec 2024 10:28:59 -0800 (PST) From: Nick Chan To: Hector Martin , Sven Peter , Alyssa Rosenzweig , "Rafael J . Wysocki" , Viresh Kumar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Asahi Linux , Linux ARM Kernel Architecture , Linux power management , Devicetree , LKML Cc: Nick Chan Subject: [PATCH v3 0/7] Apple A7-A11, T2 SoC cpufreq support Date: Thu, 19 Dec 2024 02:25:02 +0800 Message-ID: <20241218182834.22334-1-towinchenmi@gmail.com> X-Mailer: git-send-email 2.47.1 Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 This series add driver support for cpufreq Apple A7-A11, T2 SoCs. Device Tree nodes will be included in another series. Changes since v2: - Use NSEC_PER_USEC instead of 1000 as multplier. v2: https://lore.kernel.org/asahi/20241212070344.3858-1-towinchenmi@gmail.com/T Changes since v1: - transition_latency is in ns, APPLE_DVFS_TRANSITION_TIMEOUT in us. Multiply APPLE_DVFS_TRANSITION_TIMEOUT by 1000 before setting it as transition_latency. v1: https://lore.kernel.org/asahi/20241211112244.18393-1-towinchenmi@gmail.com/T Nick Chan --- Hector Martin (1): cpufreq: apple-soc: Drop setting the PS2 field on M2+ Nick Chan (6): dt-bindings: cpufreq: apple,cluster-cpufreq: Add A7-A11, T2 compatibles cpufreq: apple-soc: Allow per-SoC configuration of APPLE_DVFS_CMD_PS1 cpufreq: apple-soc: Use 32-bit read for status register cpufreq: apple-soc: Increase cluster switch timeout to 400us cpufreq: apple-soc: Set fallback transition latency to APPLE_DVFS_TRANSITION_TIMEOUT cpufreq: apple-soc: Add Apple A7-A8X SoC cpufreq support .../cpufreq/apple,cluster-cpufreq.yaml | 10 +++- drivers/cpufreq/apple-soc-cpufreq.c | 56 +++++++++++++++---- 2 files changed, 54 insertions(+), 12 deletions(-) base-commit: 78d4f34e2115b517bcbfe7ec0d018bbbb6f9b0b8