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Fri, 10 Jan 2025 07:21:23 -0800 (PST) From: Neil Armstrong Subject: [PATCH 0/4] arm64: qcom: sm8650: add DDR, LLCC & L3 CPU bandwidth scaling Date: Fri, 10 Jan 2025 16:21:17 +0100 Message-Id: <20250110-topic-sm8650-ddr-bw-scaling-v1-0-041d836b084c@linaro.org> Precedence: bulk X-Mailing-List: linux-pm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-B4-Tracking: v=1; b=H4sIAO06gWcC/x3MwQqDMAwA0F+RnBdo6izqrwwP2qYa2Ko0sgniv 694fJd3gnIWVuirEzJ/RWVNBfSowC9jmhklFIM1tjFEBvd1E4/6aV1jMISM0w/Vj29JM0ZqXR2 njuzTQRm2zFGOe38N1/UHbTvQLW0AAAA= X-Change-ID: 20250110-topic-sm8650-ddr-bw-scaling-f1863fb91246 To: Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sibi Sankar , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=939; i=neil.armstrong@linaro.org; h=from:subject:message-id; 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Signed-off-by: Neil Armstrong --- Neil Armstrong (4): dt-bindings: interconnect: OSM L3: Document sm8650 OSM L3 compatible arm64: dts: qcom: sm8650: add OSM L3 node arm64: dts: qcom: sm8650: add cpu interconnect nodes arm64: dts: qcom: add cpu OPP table with DDR, LLCC & L3 bandwidths .../bindings/interconnect/qcom,osm-l3.yaml | 1 + arch/arm64/boot/dts/qcom/sm8650.dtsi | 938 +++++++++++++++++++++ 2 files changed, 939 insertions(+) --- base-commit: 6ecd20965bdc21b265a0671ccf36d9ad8043f5ab change-id: 20250110-topic-sm8650-ddr-bw-scaling-f1863fb91246 Best regards,