From patchwork Wed Oct 10 11:42:28 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ulf Hansson X-Patchwork-Id: 1573031 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id EA3A6DFB34 for ; Wed, 10 Oct 2012 11:43:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753536Ab2JJLnT (ORCPT ); Wed, 10 Oct 2012 07:43:19 -0400 Received: from eu1sys200aog111.obsmtp.com ([207.126.144.131]:35388 "EHLO eu1sys200aog111.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752518Ab2JJLnO (ORCPT ); Wed, 10 Oct 2012 07:43:14 -0400 Received: from beta.dmz-eu.st.com ([164.129.1.35]) (using TLSv1) by eu1sys200aob111.postini.com ([207.126.147.11]) with SMTP ID DSNKUHVfSg5TRkHtmmqf7gpeo4QqzTUuv1kp@postini.com; Wed, 10 Oct 2012 11:43:14 UTC Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 52A5217B; Wed, 10 Oct 2012 11:42:55 +0000 (GMT) Received: from relay1.stm.gmessaging.net (unknown [10.230.100.17]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id B3D6929AB; Wed, 10 Oct 2012 11:42:54 +0000 (GMT) Received: from exdcvycastm003.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm003", Issuer "exdcvycastm003" (not verified)) by relay1.stm.gmessaging.net (Postfix) with ESMTPS id EF68924C07C; Wed, 10 Oct 2012 13:42:47 +0200 (CEST) Received: from steludxu1397.lud.stericsson.com (10.230.100.153) by smtp.stericsson.com (10.230.100.1) with Microsoft SMTP Server (TLS) id 8.3.83.0; Wed, 10 Oct 2012 13:42:54 +0200 From: Ulf Hansson To: , Mike Turquette , Mike Turquette , Samuel Ortiz , "Rafael J. Wysocki" Cc: , , Linus Walleij , Lee Jones , Philippe Begnic , Rickard Andersson , Jonas Aberg , Vincent Guittot , Ulf Hansson Subject: [PATCH 7/8] clk: ux500: Add armss clk and fixup smp_twd clk for u8500 Date: Wed, 10 Oct 2012 13:42:28 +0200 Message-ID: <1349869349-8070-8-git-send-email-ulf.hansson@stericsson.com> X-Mailer: git-send-email 1.7.10 In-Reply-To: <1349869349-8070-1-git-send-email-ulf.hansson@stericsson.com> References: <1349869349-8070-1-git-send-email-ulf.hansson@stericsson.com> MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Ulf Hansson The new armss clk is a prcmu_scalable_rate clk which represents the ARMSS clk. This then makes it possible to convert the smp_twd clk to a fixed factor clock type, using a fixed divider of 2 and with the armss clk as parent. Signed-off-by: Ulf Hansson --- drivers/clk/ux500/u8500_clk.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/clk/ux500/u8500_clk.c b/drivers/clk/ux500/u8500_clk.c index ca4a25e..b1bd1c46 100644 --- a/drivers/clk/ux500/u8500_clk.c +++ b/drivers/clk/ux500/u8500_clk.c @@ -205,16 +205,18 @@ void u8500_clk_init(void) clk_register_clkdev(clk, "dsilp2", "dsilink.2"); clk_register_clkdev(clk, "dsilp2", "mcde"); - clk = clk_reg_prcmu_rate("smp_twd", NULL, PRCMU_ARMSS, - CLK_IS_ROOT|CLK_GET_RATE_NOCACHE| - CLK_IGNORE_UNUSED); + clk = clk_reg_prcmu_scalable_rate("armss", NULL, + PRCMU_ARMSS, 0, CLK_IS_ROOT|CLK_IGNORE_UNUSED); + clk_register_clkdev(clk, "armss", NULL); + + clk = clk_register_fixed_factor(NULL, "smp_twd", "armss", + CLK_IGNORE_UNUSED, 1, 2); clk_register_clkdev(clk, NULL, "smp_twd"); /* * FIXME: Add special handled PRCMU clocks here: - * 1. clk_arm, use PRCMU_ARMCLK. - * 2. clkout0yuv, use PRCMU as parent + need regulator + pinctrl. - * 3. ab9540_clkout1yuv, see clkout0yuv + * 1. clkout0yuv, use PRCMU as parent + need regulator + pinctrl. + * 2. ab9540_clkout1yuv, see clkout0yuv */ /* PRCC P-clocks */