From patchwork Thu Dec 6 22:42:49 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Langsdorf X-Patchwork-Id: 1847221 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 80BB5DF2F9 for ; Thu, 6 Dec 2012 22:43:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S964978Ab2LFWmo (ORCPT ); Thu, 6 Dec 2012 17:42:44 -0500 Received: from smtp127.dfw.emailsrvr.com ([67.192.241.127]:39400 "EHLO smtp127.dfw.emailsrvr.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S964894Ab2LFWmm (ORCPT ); Thu, 6 Dec 2012 17:42:42 -0500 Received: from localhost (localhost.localdomain [127.0.0.1]) by smtp2.relay.dfw1a.emailsrvr.com (SMTP Server) with ESMTP id 27BE9783CC; Thu, 6 Dec 2012 17:42:42 -0500 (EST) X-Virus-Scanned: OK Received: by smtp2.relay.dfw1a.emailsrvr.com (Authenticated sender: mark.langsdorf-AT-calxeda.com) with ESMTPSA id E76DB7829A; Thu, 6 Dec 2012 17:42:41 -0500 (EST) From: Mark Langsdorf To: linux-kernel@vger.kernel.org, cpufreq@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Mark Langsdorf , Rob Herring Subject: [PATCH 2/6 v9] clk, highbank: Prevent glitches in non-bypass reset mode Date: Thu, 6 Dec 2012 16:42:49 -0600 Message-Id: <1354833773-22845-3-git-send-email-mark.langsdorf@calxeda.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1354833773-22845-1-git-send-email-mark.langsdorf@calxeda.com> References: <1351631056-25938-1-git-send-email-mark.langsdorf@calxeda.com> <1354833773-22845-1-git-send-email-mark.langsdorf@calxeda.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The highbank clock will glitch with the current code if the clock rate is reset without relocking the PLL. Program the PLL correctly to prevent glitches. Signed-off-by: Mark Langsdorf Signed-off-by: Rob Herring Acked-by: Mike Turquette --- Changes from v6, v7, v8 None. Changes from v5 Added Mike Turquette's ack. Changes from v4 None. Changes from v3 Changelog text and patch name now correspond to the actual patch. was clk, highbank: remove non-bypass reset mode. Changes from v2 None. Changes from v1 Removed erroneous reformating. drivers/clk/clk-highbank.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/clk-highbank.c b/drivers/clk/clk-highbank.c index 52fecad..3a0b723 100644 --- a/drivers/clk/clk-highbank.c +++ b/drivers/clk/clk-highbank.c @@ -182,8 +182,10 @@ static int clk_pll_set_rate(struct clk_hw *hwclk, unsigned long rate, reg |= HB_PLL_EXT_ENA; reg &= ~HB_PLL_EXT_BYPASS; } else { + writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg); reg &= ~HB_PLL_DIVQ_MASK; reg |= divq << HB_PLL_DIVQ_SHIFT; + writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg); } writel(reg, hbclk->reg);