From patchwork Fri Apr 12 05:55:24 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Axel Lin X-Patchwork-Id: 2434121 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id B2FABDF2A1 for ; Fri, 12 Apr 2013 05:55:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751549Ab3DLFza (ORCPT ); Fri, 12 Apr 2013 01:55:30 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:62026 "EHLO mail-pb0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751504Ab3DLFza (ORCPT ); Fri, 12 Apr 2013 01:55:30 -0400 Received: by mail-pb0-f45.google.com with SMTP id ro12so1249327pbb.4 for ; Thu, 11 Apr 2013 22:55:29 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:message-id:subject:from:to:cc:date:in-reply-to :references:content-type:x-mailer:mime-version :content-transfer-encoding:x-gm-message-state; bh=jrh4E8M6ejSEn8F4Xdx/rqJZpBeHxvrrZGU1CjWE9PQ=; b=C3fzrCR2x7KNNO9PSgeUwW9UjapZSBp8MNXJfFK+HZLngBJfGXuV9Lxhu7w/0Iz7Te xGqkQZ6dEjrHUYadYahxY0VkYi29v+4s5AVcI8Ghh52hKsCJSLru9havMY0s807YhVR4 uI/p7np3Pl816vrUIyOGqAjILJLi8Our7KXnlPeP9T5Na+RLsL1VOd6AuI7eyJ8VwY8n 9LSDns/cSGlHyw6mvPie2ouexBRiM5fCHiXL14nT6cUHqavGgd2jCPOkseYIXVjLR8Ok bnE9tKzSdDV9+SHOF/CHMzX33YK2gCVupxcHWihoMw5zEJCBzWMQy/037ri0GrX3g74s MqZg== X-Received: by 10.68.171.33 with SMTP id ar1mr12605060pbc.195.1365746129406; Thu, 11 Apr 2013 22:55:29 -0700 (PDT) Received: from [192.168.0.102] (114-40-8-210.dynamic.hinet.net. [114.40.8.210]) by mx.google.com with ESMTPS id qh4sm8060640pac.8.2013.04.11.22.55.26 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 11 Apr 2013 22:55:28 -0700 (PDT) Message-ID: <1365746124.4025.2.camel@phoenix> Subject: [RESEND][PATCH 2/3] PM / devfreq: exynos4_bus: Constify clock divider table From: Axel Lin To: "Rafael J. Wysocki" Cc: MyungJoo Ham , Kyungmin Park , Kukjin Kim , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Date: Fri, 12 Apr 2013 13:55:24 +0800 In-Reply-To: <1365746058.4025.1.camel@phoenix> References: <1365746058.4025.1.camel@phoenix> X-Mailer: Evolution 3.6.2-0ubuntu0.1 Mime-Version: 1.0 X-Gm-Message-State: ALoCoQkJF/u7ZSs65THocU716OZ3FnPzCFs1U0xdx9Es2f5tYd93vYQAd5ioGnC3zAUNo5oLXQpF Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org These tables are never modified, make them const. Signed-off-by: Axel Lin --- drivers/devfreq/exynos4_bus.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/devfreq/exynos4_bus.c b/drivers/devfreq/exynos4_bus.c index 3f37f3b..45d00d1 100644 --- a/drivers/devfreq/exynos4_bus.c +++ b/drivers/devfreq/exynos4_bus.c @@ -177,7 +177,7 @@ static unsigned int exynos4x12_int_volt[][EX4x12_LV_NUM] = { }; /*** Clock Divider Data for Exynos4210 ***/ -static unsigned int exynos4210_clkdiv_dmc0[][8] = { +static const unsigned int exynos4210_clkdiv_dmc0[][8] = { /* * Clock divider value for following * { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD @@ -191,7 +191,7 @@ static unsigned int exynos4210_clkdiv_dmc0[][8] = { /* DMC L2: 133MHz */ { 5, 1, 1, 5, 1, 1, 3, 1 }, }; -static unsigned int exynos4210_clkdiv_top[][5] = { +static const unsigned int exynos4210_clkdiv_top[][5] = { /* * Clock divider value for following * { DIVACLK200, DIVACLK100, DIVACLK160, DIVACLK133, DIVONENAND } @@ -203,7 +203,7 @@ static unsigned int exynos4210_clkdiv_top[][5] = { /* ACLK200 L2: 133MHz */ { 5, 7, 7, 7, 1 }, }; -static unsigned int exynos4210_clkdiv_lr_bus[][2] = { +static const unsigned int exynos4210_clkdiv_lr_bus[][2] = { /* * Clock divider value for following * { DIVGDL/R, DIVGPL/R } @@ -217,7 +217,7 @@ static unsigned int exynos4210_clkdiv_lr_bus[][2] = { }; /*** Clock Divider Data for Exynos4212/4412 ***/ -static unsigned int exynos4x12_clkdiv_dmc0[][6] = { +static const unsigned int exynos4x12_clkdiv_dmc0[][6] = { /* * Clock divider value for following * { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD @@ -235,7 +235,7 @@ static unsigned int exynos4x12_clkdiv_dmc0[][6] = { /* DMC L4: 100MHz */ {7, 1, 1, 7, 1, 1}, }; -static unsigned int exynos4x12_clkdiv_dmc1[][6] = { +static const unsigned int exynos4x12_clkdiv_dmc1[][6] = { /* * Clock divider value for following * { G2DACP, DIVC2C, DIVC2C_ACLK } @@ -252,7 +252,7 @@ static unsigned int exynos4x12_clkdiv_dmc1[][6] = { /* DMC L4: 100MHz */ {7, 7, 1}, }; -static unsigned int exynos4x12_clkdiv_top[][5] = { +static const unsigned int exynos4x12_clkdiv_top[][5] = { /* * Clock divider value for following * { DIVACLK266_GPS, DIVACLK100, DIVACLK160, @@ -270,7 +270,7 @@ static unsigned int exynos4x12_clkdiv_top[][5] = { /* ACLK_GDL/R L4: 100MHz */ {7, 7, 7, 7, 1}, }; -static unsigned int exynos4x12_clkdiv_lr_bus[][2] = { +static const unsigned int exynos4x12_clkdiv_lr_bus[][2] = { /* * Clock divider value for following * { DIVGDL/R, DIVGPL/R } @@ -287,7 +287,7 @@ static unsigned int exynos4x12_clkdiv_lr_bus[][2] = { /* ACLK_GDL/R L4: 100MHz */ {7, 1}, }; -static unsigned int exynos4x12_clkdiv_sclkip[][3] = { +static const unsigned int exynos4x12_clkdiv_sclkip[][3] = { /* * Clock divider value for following * { DIVMFC, DIVJPEG, DIVFIMC0~3}