@@ -88,6 +88,7 @@
#define EXYNOS_TMU_CLEAR_FALL_INT (0x111 << 12)
#define EXYNOS_TMU_TRIP_MODE_SHIFT 13
#define EXYNOS_TMU_TRIP_MODE_MASK 0x7
+#define EXYNOS_TMU_THERM_TRIP_EN_SHIFT 12
#define EXYNOS_TMU_INTEN_RISE0_SHIFT 0
#define EXYNOS_TMU_INTEN_RISE1_SHIFT 4
@@ -190,7 +191,7 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
{
struct exynos_tmu_data *data = platform_get_drvdata(pdev);
struct exynos_tmu_platform_data *pdata = data->pdata;
- unsigned int status, trim_info;
+ unsigned int status, trim_info, con;
unsigned int rising_threshold = 0, falling_threshold = 0;
int ret = 0, threshold_code, i, trigger_levs = 0;
@@ -255,6 +256,11 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
falling_threshold |=
threshold_code << 8 * i;
}
+ if (pdata->trigger_type[i] != HW_TRIP)
+ continue;
+ con = readl(data->base + EXYNOS_TMU_REG_CONTROL);
+ con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT);
+ writel(con, data->base + EXYNOS_TMU_REG_CONTROL);
}
writel(rising_threshold,
@@ -64,6 +64,7 @@ struct exynos_tmu_platform_data const exynos5250_default_tmu_data = {
.trigger_levels[0] = 85,
.trigger_levels[1] = 103,
.trigger_levels[2] = 110,
+ .trigger_levels[3] = 120,
.trigger_enable[0] = 1,
.trigger_enable[1] = 1,
.trigger_enable[2] = 1,
@@ -71,6 +72,7 @@ struct exynos_tmu_platform_data const exynos5250_default_tmu_data = {
.trigger_type[0] = 0,
.trigger_type[1] = 0,
.trigger_type[2] = 1,
+ .trigger_type[3] = 2,
.gain = 8,
.reference_voltage = 16,
.noise_cancel_mode = 4,