From patchwork Mon Jun 17 06:46:20 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kachhap X-Patchwork-Id: 2731361 X-Patchwork-Delegate: eduardo.valentin@ti.com Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 2B71A9F39E for ; Mon, 17 Jun 2013 06:53:23 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D52A6201FA for ; Mon, 17 Jun 2013 06:53:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DB5BC20177 for ; Mon, 17 Jun 2013 06:53:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932373Ab3FQGr7 (ORCPT ); Mon, 17 Jun 2013 02:47:59 -0400 Received: from mail-pa0-f46.google.com ([209.85.220.46]:64567 "EHLO mail-pa0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932359Ab3FQGrx (ORCPT ); Mon, 17 Jun 2013 02:47:53 -0400 Received: by mail-pa0-f46.google.com with SMTP id fa11so2521444pad.5 for ; Sun, 16 Jun 2013 23:47:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=WniF89SPyFlvzatdvddrafnJlHU4p6DGNa7D/M9spL4=; b=iErz+HsnxbNuJgDn40YXYzX6AHvHjgou4ngtAMx7gu5vwJhbdNlnZgqBzJJUvR6MC0 giXHOPGN9v6lIlhdr5AUkggvgMUoAGEGiMljB3ll8f2/Ut4xncQOGYGAIArS0JAzhUaW lF/l/U67pkqXv2R9q/MKNfDDoT3b0RwzwjmVcrqiNehhfthkL6cP4XnGe3+zm5A9iw+7 0VSxAui887NHKTML9B0tZMiLnwo27ybfHp4Hz+KkEK+zgLdywrITB56VNKpi/XtTvOaq eokB0IXOlkTFgMeJiNVnm3/tS1LQEtmpug/g84Eo6h5R9wBu3WPQRmoTQ22L96QHgy+s 6sIQ== X-Received: by 10.68.241.193 with SMTP id wk1mr3108466pbc.5.1371451672829; Sun, 16 Jun 2013 23:47:52 -0700 (PDT) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPSA id xl3sm11639859pbb.17.2013.06.16.23.47.48 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Sun, 16 Jun 2013 23:47:51 -0700 (PDT) From: Amit Daniel Kachhap To: linux-pm@vger.kernel.org, Zhang Rui , Eduardo Valentin Cc: linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, amit.kachhap@gmail.com, Kukjin Kim , jonghwa3.lee@samsung.com Subject: [PATCH V6 11/30] thermal: exynos: Support thermal tripping Date: Mon, 17 Jun 2013 12:16:20 +0530 Message-Id: <1371451599-31035-12-git-send-email-amit.daniel@samsung.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1371451599-31035-1-git-send-email-amit.daniel@samsung.com> References: <1371451599-31035-1-git-send-email-amit.daniel@samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP TMU urgently sends active-high signal (thermal trip) to PMU, and thermal tripping by hardware logic. Thermal tripping means that PMU cuts off the whole power of SoC by controlling external voltage regulator. Acked-by: Kukjin Kim Acked-by: Jonghwa Lee Signed-off-by: Jonghwan Choi Signed-off-by: Amit Daniel Kachhap Acked-by: Eduardo Valentin --- drivers/thermal/samsung/exynos_tmu.c | 45 +++++++++++++++++++++++++--- drivers/thermal/samsung/exynos_tmu_data.c | 2 + drivers/thermal/samsung/exynos_tmu_data.h | 2 + 3 files changed, 44 insertions(+), 5 deletions(-) diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c index 6fd776f..33f494e 100644 --- a/drivers/thermal/samsung/exynos_tmu.c +++ b/drivers/thermal/samsung/exynos_tmu.c @@ -117,7 +117,7 @@ static int exynos_tmu_initialize(struct platform_device *pdev) struct exynos_tmu_data *data = platform_get_drvdata(pdev); struct exynos_tmu_platform_data *pdata = data->pdata; const struct exynos_tmu_registers *reg = pdata->registers; - unsigned int status, trim_info; + unsigned int status, trim_info = 0, con; unsigned int rising_threshold = 0, falling_threshold = 0; int ret = 0, threshold_code, i, trigger_levs = 0; @@ -144,10 +144,26 @@ static int exynos_tmu_initialize(struct platform_device *pdev) (data->temp_error2 != 0)) data->temp_error1 = pdata->efuse_value; - /* Count trigger levels to be enabled */ - for (i = 0; i < MAX_THRESHOLD_LEVS; i++) - if (pdata->trigger_levels[i]) + if (pdata->max_trigger_level > MAX_THRESHOLD_LEVS) { + dev_err(&pdev->dev, "Invalid max trigger level\n"); + goto out; + } + + for (i = 0; i < pdata->max_trigger_level; i++) { + if (!pdata->trigger_levels[i]) + continue; + + if ((pdata->trigger_type[i] == HW_TRIP) && + (!pdata->trigger_levels[pdata->max_trigger_level - 1])) { + dev_err(&pdev->dev, "Invalid hw trigger level\n"); + ret = -EINVAL; + goto out; + } + + /* Count trigger levels except the HW trip*/ + if (!(pdata->trigger_type[i] == HW_TRIP)) trigger_levs++; + } if (data->soc == SOC_ARCH_EXYNOS4210) { /* Write temperature code for threshold */ @@ -165,7 +181,8 @@ static int exynos_tmu_initialize(struct platform_device *pdev) writel(reg->inten_rise_mask, data->base + reg->tmu_intclear); } else if (data->soc == SOC_ARCH_EXYNOS) { /* Write temperature code for rising and falling threshold */ - for (i = 0; i < trigger_levs; i++) { + for (i = 0; + i < trigger_levs && i < EXYNOS_MAX_TRIGGER_PER_REG; i++) { threshold_code = temp_to_code(data, pdata->trigger_levels[i]); if (threshold_code < 0) { @@ -191,6 +208,24 @@ static int exynos_tmu_initialize(struct platform_device *pdev) writel((reg->inten_rise_mask << reg->inten_rise_shift) | (reg->inten_fall_mask << reg->inten_fall_shift), data->base + reg->tmu_intclear); + + /* if last threshold limit is also present */ + i = pdata->max_trigger_level - 1; + if (pdata->trigger_levels[i] && + (pdata->trigger_type[i] == HW_TRIP)) { + threshold_code = temp_to_code(data, + pdata->trigger_levels[i]); + if (threshold_code < 0) { + ret = threshold_code; + goto out; + } + rising_threshold |= threshold_code << 8 * i; + writel(rising_threshold, + data->base + reg->threshold_th0); + con = readl(data->base + reg->tmu_ctrl); + con |= (1 << reg->therm_trip_en_shift); + writel(con, data->base + reg->tmu_ctrl); + } } out: clk_disable(data->clk); diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c index 589a519..e7cb1cc 100644 --- a/drivers/thermal/samsung/exynos_tmu_data.c +++ b/drivers/thermal/samsung/exynos_tmu_data.c @@ -123,6 +123,7 @@ struct exynos_tmu_platform_data const exynos5250_default_tmu_data = { .trigger_levels[0] = 85, .trigger_levels[1] = 103, .trigger_levels[2] = 110, + .trigger_levels[3] = 120, .trigger_enable[0] = 1, .trigger_enable[1] = 1, .trigger_enable[2] = 1, @@ -130,6 +131,7 @@ struct exynos_tmu_platform_data const exynos5250_default_tmu_data = { .trigger_type[0] = THROTTLE_ACTIVE, .trigger_type[1] = THROTTLE_ACTIVE, .trigger_type[2] = SW_TRIP, + .trigger_type[3] = HW_TRIP, .max_trigger_level = 4, .gain = 8, .reference_voltage = 16, diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h index 0e2244f..4acf070 100644 --- a/drivers/thermal/samsung/exynos_tmu_data.h +++ b/drivers/thermal/samsung/exynos_tmu_data.h @@ -91,6 +91,8 @@ #define EXYNOS_EMUL_DATA_MASK 0xFF #define EXYNOS_EMUL_ENABLE 0x1 +#define EXYNOS_MAX_TRIGGER_PER_REG 4 + #if defined(CONFIG_CPU_EXYNOS4210) extern struct exynos_tmu_platform_data const exynos4210_default_tmu_data; #define EXYNOS4210_TMU_DRV_DATA (&exynos4210_default_tmu_data)