From patchwork Tue Aug 20 05:17:44 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Zhang X-Patchwork-Id: 2846842 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 2A1B09F2F4 for ; Tue, 20 Aug 2013 05:23:33 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 53CA62034D for ; Tue, 20 Aug 2013 05:23:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 74FA920328 for ; Tue, 20 Aug 2013 05:23:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751831Ab3HTFXO (ORCPT ); Tue, 20 Aug 2013 01:23:14 -0400 Received: from na3sys009aog137.obsmtp.com ([74.125.149.18]:55564 "EHLO na3sys009aog137.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751856Ab3HTFXM (ORCPT ); Tue, 20 Aug 2013 01:23:12 -0400 Received: from sc-owa02.marvell.com ([199.233.58.137]) (using TLSv1) by na3sys009aob137.postini.com ([74.125.148.12]) with SMTP ID DSNKUhL9P6WABAWzwCLTqx3olB9pY1M3Hsg+@postini.com; Mon, 19 Aug 2013 22:23:12 PDT Received: from maili.marvell.com (10.93.76.43) by sc-owa02.marvell.com (10.93.76.22) with Microsoft SMTP Server id 8.3.213.0; Mon, 19 Aug 2013 22:17:47 -0700 Received: from localhost (unknown [10.38.164.239]) by maili.marvell.com (Postfix) with ESMTP id 0C11E1CCDAE; Mon, 19 Aug 2013 22:17:47 -0700 (PDT) From: Neil Zhang To: , CC: , , Neil Zhang Subject: [PATCH] cpuidle: coupled: fix dead loop corner case Date: Tue, 20 Aug 2013 13:17:44 +0800 Message-ID: <1376975864-31487-1-git-send-email-zhangwm@marvell.com> X-Mailer: git-send-email 1.7.4.1 MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-9.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP There is a corener case when no peripheral irqs route to secondary cores. Let's take dual core system for example, the sequence is as following: Core 0 Core1 1. set waiting bit and enter waiting loop 2. set waiting bit and poke core1 3. clear poke in irq and enter safe state 4. set ready bit and enter ready loop Since there is no peripheral irq route to core 1, so it will stay in safe state forever, and core 0 will dead loop in the following code. while (!cpuidle_coupled_cpus_ready(coupled)) { /* Check if any other cpus bailed out of idle. */ if (!cpuidle_coupled_cpus_waiting(coupled)) } The solution is don't let secondary core enter safe state when it has already handled the poke interrupt. Signed-off-by: Neil Zhang Reviewed-by: Fangsuo Wu --- drivers/cpuidle/coupled.c | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/drivers/cpuidle/coupled.c b/drivers/cpuidle/coupled.c index 2a297f8..a37c718 100644 --- a/drivers/cpuidle/coupled.c +++ b/drivers/cpuidle/coupled.c @@ -119,6 +119,7 @@ struct cpuidle_coupled { #define CPUIDLE_COUPLED_NOT_IDLE (-1) static DEFINE_MUTEX(cpuidle_coupled_lock); +static DEFINE_PER_CPU(bool, poke_sync); static DEFINE_PER_CPU(struct call_single_data, cpuidle_coupled_poke_cb); /* @@ -295,6 +296,7 @@ static void cpuidle_coupled_poked(void *info) { int cpu = (unsigned long)info; cpumask_clear_cpu(cpu, &cpuidle_coupled_poked_mask); + __this_cpu_write(poke_sync, true); } /** @@ -473,6 +475,7 @@ retry: * allowed for a single cpu. */ while (!cpuidle_coupled_cpus_waiting(coupled)) { + __this_cpu_write(poke_sync, false); if (cpuidle_coupled_clear_pokes(dev->cpu)) { cpuidle_coupled_set_not_waiting(dev->cpu, coupled); goto out; @@ -483,6 +486,10 @@ retry: goto out; } + if (cpuidle_coupled_cpus_waiting(coupled) + && __this_cpu_read(poke_sync)) + break; + entered_state = cpuidle_enter_state(dev, drv, dev->safe_state_index); }