From patchwork Wed Sep 18 10:58:11 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sudeep KarkadaNagesha X-Patchwork-Id: 2905481 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id CEC079F1BF for ; Wed, 18 Sep 2013 11:02:04 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1ECFB20322 for ; Wed, 18 Sep 2013 11:02:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 496BF20326 for ; Wed, 18 Sep 2013 11:01:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751903Ab3IRLBy (ORCPT ); Wed, 18 Sep 2013 07:01:54 -0400 Received: from cam-admin0.cambridge.arm.com ([217.140.96.50]:60650 "EHLO cam-admin0.cambridge.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751818Ab3IRLBy (ORCPT ); Wed, 18 Sep 2013 07:01:54 -0400 Received: from e103737-lin.cambridge.arm.com (e103737-lin.cambridge.arm.com [10.1.207.49]) by cam-admin0.cambridge.arm.com (8.12.6/8.12.6) with ESMTP id r8IAvvkj012051; Wed, 18 Sep 2013 11:57:57 +0100 (BST) From: Sudeep KarkadaNagesha To: linux-pm@vger.kernel.org, devicetree@vger.kernel.org Cc: Sudeep.KarkadaNagesha@arm.com, Sudeep KarkadaNagesha , Rob Herring , Pawel Moll , Mark Rutland , Kumar Gala , Stephen Warren , "Rafael J. Wysocki" , Nishanth Menon Subject: [PATCH 1/3] PM / OPP: extend DT binding to specify phandle of another node for OPP Date: Wed, 18 Sep 2013 11:58:11 +0100 Message-Id: <1379501893-12669-2-git-send-email-Sudeep.KarkadaNagesha@arm.com> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1379501893-12669-1-git-send-email-Sudeep.KarkadaNagesha@arm.com> References: <1379501893-12669-1-git-send-email-Sudeep.KarkadaNagesha@arm.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-4.0 required=5.0 tests=BAYES_00,KHOP_BIG_TO_CC, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Sudeep KarkadaNagesha If more than one similar devices share the same operating points(OPPs) being in the same clock domain, currently we need to replicate the OPP entries in all the nodes. This patch extends existing binding by adding a new property named 'operating-points-phandle' to specify the phandle in any device node pointing to another node which contains the actual OPP tuples. This helps to avoid replication if multiple devices share the OPPs. Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Kumar Gala Cc: Stephen Warren Cc: "Rafael J. Wysocki" Cc: Nishanth Menon Signed-off-by: Sudeep KarkadaNagesha --- Documentation/devicetree/bindings/power/opp.txt | 152 ++++++++++++++++++++++-- 1 file changed, 140 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/power/opp.txt b/Documentation/devicetree/bindings/power/opp.txt index 74499e5..e9fea65 100644 --- a/Documentation/devicetree/bindings/power/opp.txt +++ b/Documentation/devicetree/bindings/power/opp.txt @@ -4,22 +4,150 @@ SoCs have a standard set of tuples consisting of frequency and voltage pairs that the device will support per voltage domain. These are called Operating Performance Points or OPPs. -Properties: +Required Properties: - operating-points: An array of 2-tuples items, and each item consists of frequency and voltage like . freq: clock frequency in kHz vol: voltage in microvolt +Optional properties: +- operating-points-phandle: phandle to the device tree node which contains + the operating points tuples(recommended to be used if multiple + devices are in the same clock domain and hence share OPPs, as it + avoids replication of OPPs) + Examples: -cpu@0 { - compatible = "arm,cortex-a9"; - reg = <0>; - next-level-cache = <&L2>; - operating-points = < - /* kHz uV */ - 792000 1100000 - 396000 950000 - 198000 850000 - >; -}; +1. A uniprocessor system (phandle not required) + + cpu0: cpu@0 { + compatible = "arm,cortex-a9"; + reg = <0>; + operating-points = < + /* kHz uV */ + 792000 1100000 + 396000 950000 + 198000 850000 + >; + }; + +If more than one device of same type share the same OPPs, for example +all the CPUs on a SoC or in a single cluster on a SoC, then we need to +avoid replicating the OPPs in all the nodes. We can specify the phandle +of the node which contains the OPP tuples + +2a. Consider a SMP system with 4 CPUs in the same clock domain + (backward compatible style, only CPU0 contains OPP) + + cpu0: cpu@0 { + compatible = "arm,cortex-a9"; + reg = <0>; + operating-points = < + /* kHz uV */ + 792000 1100000 + 396000 950000 + 198000 850000 + >; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a9"; + reg = <1>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a9"; + reg = <2>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a9"; + reg = <3>; + }; + +2b. Consider a SMP system with 4 CPUs in the same clock domain + (using operating-points-phandle) + + cpu0: cpu@0 { + compatible = "arm,cortex-a9"; + reg = <0>; + operating-points-phandle = <&cpu_opp>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a9"; + reg = <1>; + operating-points-phandle = <&cpu_opp>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a9"; + reg = <2>; + operating-points-phandle = <&cpu_opp>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a9"; + reg = <3>; + operating-points-phandle = <&cpu_opp>; + }; + + operating_points { + cpu_opp: cpu_opp { + operating-points = < + /* kHz uV */ + 792000 1100000 + 396000 950000 + 198000 850000 + >; + }; + ... /* other device OPP nodes */ + } + +3. Consider an AMP(asymmetric multi-processor) sytem with 2 clusters of CPUs. + Each cluster has 2 CPUs and all the CPUs within the cluster share the clock + domain. + + cpu0: cpu@0 { + compatible = "arm,cortex-a15"; + reg = <0>; + operating-points-phandle = <&cluster0_opp>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a15"; + reg = <1>; + operating-points-phandle = <&cluster0_opp>; + }; + + cpu2: cpu@100 { + compatible = "arm,cortex-a7"; + reg = <100>; + operating-points-phandle = <&cluster1_opp>; + }; + + cpu3: cpu@101 { + compatible = "arm,cortex-a7"; + reg = <101>; + operating-points-phandle = <&cluster1_opp>; + }; + + operating_points { + cluster0_opp: cluster0_opp { + operating-points = < + /* kHz uV */ + 792000 1100000 + 396000 950000 + 198000 850000 + >; + }; + cluster1_opp: cluster1_opp { + operating-points = < + /* kHz uV */ + 792000 950000 + 396000 750000 + 198000 450000 + >; + }; + ... /* other device OPP nodes */ + }