From patchwork Mon Oct 14 13:58:23 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 3036621 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 1D27DBF924 for ; Mon, 14 Oct 2013 13:59:14 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 409B62023F for ; Mon, 14 Oct 2013 13:59:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E7EEE20253 for ; Mon, 14 Oct 2013 13:59:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756731Ab3JNN7C (ORCPT ); Mon, 14 Oct 2013 09:59:02 -0400 Received: from top.free-electrons.com ([176.31.233.9]:60851 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1756642Ab3JNN66 (ORCPT ); Mon, 14 Oct 2013 09:58:58 -0400 Received: by mail.free-electrons.com (Postfix, from userid 106) id 8EC1E828; Mon, 14 Oct 2013 15:59:02 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,KHOP_BIG_TO_CC, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from localhost (tra42-5-83-152-246-54.fbx.proxad.net [83.152.246.54]) by mail.free-electrons.com (Postfix) with ESMTPSA id D20C9ECC; Mon, 14 Oct 2013 15:59:00 +0200 (CEST) From: Gregory CLEMENT To: Daniel Lezcano , "Rafael J. Wysocki" , linux-pm@vger.kernel.org, lorenzo.pieralisi@arm.com, Jason Cooper , Andrew Lunn , Gregory CLEMENT Cc: Thomas Petazzoni , Ezequiel Garcia , Sebastian Hesselbarth , linux-arm-kernel@lists.infradead.org, Nicolas Pitre , Lior Amsalem , Maen Suleiman , Tawfik Bayouk , Shadi Ammouri , Eran Ben-Avi , Yehuda Yitschak , Nadav Haklai , Ike Pan , Dan Frazier , Leif Lindholm , Jon Masters , David Marlin Subject: [PATCH v3 11/14] ARM: mvebu: Add CPU idle low level support for Marvell Armada XP Date: Mon, 14 Oct 2013 15:58:23 +0200 Message-Id: <1381759106-15004-12-git-send-email-gregory.clement@free-electrons.com> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1381759106-15004-1-git-send-email-gregory.clement@free-electrons.com> References: <1381759106-15004-1-git-send-email-gregory.clement@free-electrons.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Level: * X-Virus-Scanned: ClamAV using ClamSMTP This commit adds the low level implementation of CPU Idle. Currently only Armada XP is supported, but the support will be extended for Armada 370. Based on the work of Nadav Haklai. Signed-off-by: Nadav Haklai Signed-off-by: Gregory CLEMENT --- arch/arm/mach-mvebu/Makefile | 1 + arch/arm/mach-mvebu/suspend-armada-370-xp.S | 90 +++++++++++++++++++++++++++++ 2 files changed, 91 insertions(+) create mode 100644 arch/arm/mach-mvebu/suspend-armada-370-xp.S diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile index 2d04f0e..9cd2705 100644 --- a/arch/arm/mach-mvebu/Makefile +++ b/arch/arm/mach-mvebu/Makefile @@ -8,3 +8,4 @@ obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o obj-$(CONFIG_ARCH_MVEBU) += coherency.o coherency_ll.o pmsu.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o +obj-$(CONFIG_ARM_ARMADA_370_XP_CPUIDLE) += suspend-armada-370-xp.o diff --git a/arch/arm/mach-mvebu/suspend-armada-370-xp.S b/arch/arm/mach-mvebu/suspend-armada-370-xp.S new file mode 100644 index 0000000..5f01a68 --- /dev/null +++ b/arch/arm/mach-mvebu/suspend-armada-370-xp.S @@ -0,0 +1,90 @@ +/* + * CPU idle low level implementation for Marvell Armada 370 and Armada XP SoCs + * + * Copyright (C) 2013 Marvell + * + * Nadav Haklai + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + */ +#include + +/* +* armadaxp_cpu_suspend: enter cpu deepIdle state +* input: +*/ +ENTRY(armada_370_xp_cpu_suspend) +/* Save ARM registers */ + stmfd sp!, {r4 - r11, lr} @ save registers on stack + + bl armada_370_xp_pmsu_idle_prepare + /* + * Invalidate L1 data cache. Even though only invalidate is + * necessary exported flush API is used here. Doing clean + * on already clean cache would be almost NOP. + */ + bl v7_flush_dcache_all + + /* + * Clear the SCTLR.C bit to prevent further data cache + * allocation. Clearing SCTLR.C would make all the data accesses + * strongly ordered and would not hit the cache. + */ + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #(1 << 2) @ Disable the C bit + mcr p15, 0, r0, c1, c0, 0 + isb + + bl v7_flush_dcache_all + + /* Data memory barrier and Data sync barrier */ + dsb + dmb + + bl armada_370_xp_disable_snoop_ena + + dsb @ Data Synchronization Barrier + +/* + * =================================== + * == WFI instruction => Enter idle == + * =================================== + */ + + wfi @ wait for interrupt +/* + * =================================== + * == Resume path for non-OFF modes == + * =================================== + */ + +/* Enable SnoopEna - Exclusive */ + mov r0, #1 @ r0!=0 means use virtual address + mov r1, #0 @ Do not add CPU to SMP group + bl ll_set_cpu_coherent + +/* Re-enable C-bit if needed */ + mrc p15, 0, r0, c1, c0, 0 + tst r0, #(1 << 2) @ Check C bit enabled? + orreq r0, r0, #(1 << 2) @ Enable the C bit if cleared + mcreq p15, 0, r0, c1, c0, 0 + isb + + ldmfd sp!, {r4 - r11, pc} @ restore regs and return +ENDPROC(armada_370_xp_cpu_suspend) + +/* +* armada_370_xp_cpu_resume: exit cpu deepIdle state +*/ +ENTRY(armada_370_xp_cpu_resume) + mov r0, #0 @ r0==0 means use physical address + mov r1, #1 @ Add CPU to SMP group + bl ll_set_cpu_coherent + + /* Now branch to the common CPU resume function */ + b cpu_resume + +ENDPROC(armada_370_xp_cpu_resume)