@@ -7,14 +7,16 @@ Required properties:
- compatible: "marvell,armada-370-xp-pmsu"
- reg: Should contain PMSU registers location and length. First pair
- for the per-CPU SW Reset Control registers, second pair for the
- Power Management Service Unit.
+ for the per-CPU SW Reset Control registers, second pair for the CPU
+ Power Management Service Unit registers, third pair for the Fabric Power
+ Management Service Unit registers.
Example:
-armada-370-xp-pmsu@d0022000 {
+armada-370-xp-pmsu@22000 {
compatible = "marvell,armada-370-xp-pmsu";
- reg = <0xd0022100 0x430>,
- <0xd0020800 0x20>;
+ reg = <0x22100 0x430>,
+ <0x20800 0x20>,
+ <0x22000 0x24>;
};
@@ -48,7 +48,7 @@
armada-370-xp-pmsu@22000 {
compatible = "marvell,armada-370-xp-pmsu";
- reg = <0x22100 0x430>, <0x20800 0x20>;
+ reg = <0x22100 0x430>, <0x20800 0x20>, <0x22000 0x24>;
};
serial@12200 {
The Power Management Unit Service block also controls the Coherency Fabric subsystem. This new set of registers is needed for the CPU idle implementation for the Armada XP, it allows to enter in a deep CPU idle state where the Coherency Fabric and the L2 cache are powerdown. Cc: devicetree@vger.kernel.org Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> --- Documentation/devicetree/bindings/arm/armada-370-xp-pmsu.txt | 12 +++++++----- arch/arm/boot/dts/armada-xp.dtsi | 2 +- 2 files changed, 8 insertions(+), 6 deletions(-)