From patchwork Tue Nov 12 13:53:09 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas KANDAGATLA X-Patchwork-Id: 3172891 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 077AE9F3A0 for ; Tue, 12 Nov 2013 14:21:09 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 72413204EC for ; Tue, 12 Nov 2013 14:21:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id E27EB20377 for ; Tue, 12 Nov 2013 14:21:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754349Ab3KLOU7 (ORCPT ); Tue, 12 Nov 2013 09:20:59 -0500 Received: from eu1sys200aog125.obsmtp.com ([207.126.144.159]:35116 "EHLO eu1sys200aog125.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753878Ab3KLOU6 (ORCPT ); Tue, 12 Nov 2013 09:20:58 -0500 X-Greylist: delayed 1592 seconds by postgrey-1.27 at vger.kernel.org; Tue, 12 Nov 2013 09:20:56 EST Received: from beta.dmz-eu.st.com ([164.129.1.35]) (using TLSv1) by eu1sys200aob125.postini.com ([207.126.147.11]) with SMTP ID DSNKUoI5R8NTK3kv/wO1UCTpEvILofUsBu2L@postini.com; Tue, 12 Nov 2013 14:20:57 UTC Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 6B31EC3; Tue, 12 Nov 2013 13:53:18 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas24.st.com [10.75.90.94]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id C4C5F5426; Tue, 12 Nov 2013 13:40:26 +0000 (GMT) Received: from localhost (10.65.51.59) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.123.3; Tue, 12 Nov 2013 14:53:49 +0100 From: To: , Cc: Rob Herring , Pawel Moll , Mark Rutland , Stephen Warren , Ian Campbell , Rob Landley , Russell King , Srinivas Kandagatla , Stuart Menefy , Pavel Machek , "Rafael J. Wysocki" , Len Brown , , Greg Kroah-Hartman , Giuseppe Cavallaro , Grant Likely , , , , , Subject: [PATCH RFC 09/10] ARM: STi: Add STiH415 ethernet support. Date: Tue, 12 Nov 2013 13:53:09 +0000 Message-ID: <1384264389-7697-1-git-send-email-srinivas.kandagatla@st.com> X-Mailer: git-send-email 1.7.6.5 In-Reply-To: <1384264311-7308-1-git-send-email-srinivas.kandagatla@st.com> References: <1384264311-7308-1-git-send-email-srinivas.kandagatla@st.com> MIME-Version: 1.0 X-Originating-IP: [10.65.51.59] Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Srinivas Kandagatla This patch adds support to STiH415 SOC, which has two ethernet snps,dwmac controllers version 3.610. With this patch B2000 and B2020 boards can boot with ethernet in MII and RGMII modes. Tested on both B2020 and B2000. Signed-off-by: Srinivas Kandagatla --- arch/arm/boot/dts/stih415-clock.dtsi | 14 +++++ arch/arm/boot/dts/stih415-pinctrl.dtsi | 82 ++++++++++++++++++++++++++++++++ arch/arm/boot/dts/stih415.dtsi | 56 ++++++++++++++++++++++ arch/arm/boot/dts/stih41x-b2000.dtsi | 32 ++++++++++++ arch/arm/boot/dts/stih41x-b2020.dtsi | 33 +++++++++++++ 5 files changed, 217 insertions(+), 0 deletions(-) diff --git a/arch/arm/boot/dts/stih415-clock.dtsi b/arch/arm/boot/dts/stih415-clock.dtsi index 174c799..d047dbc 100644 --- a/arch/arm/boot/dts/stih415-clock.dtsi +++ b/arch/arm/boot/dts/stih415-clock.dtsi @@ -34,5 +34,19 @@ compatible = "fixed-clock"; clock-frequency = <100000000>; }; + + CLKS_GMAC0_PHY: clockgenA1@7 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + clock-output-names = "CLKS_GMAC0_PHY"; + }; + + CLKS_ETH1_PHY: clockgenA0@7 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <25000000>; + clock-output-names = "CLKS_ETH1_PHY"; + }; }; }; diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi index 1d322b2..c087af8 100644 --- a/arch/arm/boot/dts/stih415-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih415-pinctrl.dtsi @@ -86,6 +86,57 @@ }; }; }; + + gmac1 { + pinctrl_mii1: mii1 { + st,pins { + txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>; + col = <&PIO0 7 ALT1 IN BYPASS 1000>; + mdio = <&PIO1 0 ALT1 OUT BYPASS 0>; + mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>; + crs = <&PIO1 2 ALT1 IN BYPASS 1000>; + mdint = <&PIO1 3 ALT1 IN BYPASS 0>; + rxd0 = <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rxd1 = <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rxd2 = <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rxd3 = <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rxdv = <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>; + phyclk = <&PIO2 3 ALT1 IN NICLK 1000 CLK_A>; + }; + }; + + pinctrl_rgmii1: rgmii1-0 { + st,pins { + txd0 = <&PIO0 0 ALT1 OUT DE_IO 1000 CLK_A>; + txd1 = <&PIO0 1 ALT1 OUT DE_IO 1000 CLK_A>; + txd2 = <&PIO0 2 ALT1 OUT DE_IO 1000 CLK_A>; + txd3 = <&PIO0 3 ALT1 OUT DE_IO 1000 CLK_A>; + txen = <&PIO0 5 ALT1 OUT DE_IO 0 CLK_A>; + txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>; + mdio = <&PIO1 0 ALT1 OUT BYPASS 0>; + mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>; + rxd0 = <&PIO1 4 ALT1 IN DE_IO 0 CLK_A>; + rxd1 = <&PIO1 5 ALT1 IN DE_IO 0 CLK_A>; + rxd2 = <&PIO1 6 ALT1 IN DE_IO 0 CLK_A>; + rxd3 = <&PIO1 7 ALT1 IN DE_IO 0 CLK_A>; + + rxdv = <&PIO2 0 ALT1 IN DE_IO 500 CLK_A>; + rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>; + phyclk = <&PIO2 3 ALT4 OUT NICLK 0 CLK_B>; + + clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>; + }; + }; + }; + }; pin-controller-front { @@ -197,6 +248,37 @@ }; }; }; + + gmac0{ + pinctrl_mii0: mii0 { + st,pins { + mdint = <&PIO13 6 ALT2 IN BYPASS 0>; + txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>; + + txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>; + txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; + txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>; + txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>; + + txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>; + txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; + crs = <&PIO15 2 ALT2 IN BYPASS 1000>; + col = <&PIO15 3 ALT2 IN BYPASS 1000>; + mdio = <&PIO15 4 ALT2 OUT BYPASS 3000>; + mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>; + + rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; + rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; + rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; + rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>; + rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>; + rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>; + rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>; + phyclk = <&PIO13 5 ALT2 OUT NICLK 1000 CLK_A>; + + }; + }; + }; }; pin-controller-left { diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi index 0c0776e..c2b18c8 100644 --- a/arch/arm/boot/dts/stih415.dtsi +++ b/arch/arm/boot/dts/stih415.dtsi @@ -94,5 +94,61 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sbc_serial1>; }; + + ethernet0: ethernet0{ + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + compatible = "st,stih415-dwmac"; + reg = <0x148 0x4>; + st,syscon = <&syscfg_rear>; + resets = <&softreset STIH415_ETH0_SOFTRESET>; + ranges; + + dwmac0:dwmac@fe810000 { + device_type = "network"; + compatible = "snps,dwmac", "snps,dwmac-3.610"; + status = "disabled"; + reg = <0xfe810000 0x8000>; + interrupts = <0 147 0>, <0 148 0>, <0 149 0>; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; + + snps,pbl = <32>; + snps,mixed-burst; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mii0>; + clock-names = "stmmaceth"; + clocks = <&CLKS_GMAC0_PHY>; + }; + }; + + ethernet1: ethernet1 { + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + compatible = "st,stih415-dwmac"; + reg = <0x74 0x4>; + st,syscon = <&syscfg_sbc>; + resets = <&softreset STIH415_ETH1_SOFTRESET>; + ranges; + + dwmac1: dwmac@fef08000 { + device_type = "network"; + compatible = "snps,dwmac", "snps,dwmac-3.610"; + status = "disabled"; + reg = <0xfef08000 0x8000>; + interrupts = <0 150 0>, <0 151 0>, <0 152 0>; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; + + snps,pbl = <32>; + snps,mixed-burst; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mii1>; + clock-names = "stmmaceth"; + clocks = <&CLKS_ETH1_PHY>; + }; + }; }; }; diff --git a/arch/arm/boot/dts/stih41x-b2000.dtsi b/arch/arm/boot/dts/stih41x-b2000.dtsi index 8e694d2..9ae9ca9 100644 --- a/arch/arm/boot/dts/stih41x-b2000.dtsi +++ b/arch/arm/boot/dts/stih41x-b2000.dtsi @@ -20,6 +20,8 @@ aliases { ttyAS0 = &serial2; + ethernet0 = &dwmac0; + ethernet1 = &dwmac1; }; soc { @@ -37,5 +39,35 @@ }; }; + ethernet0: ethernet0{ + status = "okay"; + st,tx-retime-src = "txclk"; + + dwmac0:dwmac@fe810000 { + status = "okay"; + phy-mode = "mii"; + snps,phy-addr = <0x1>; + + snps,reset-gpio = <&PIO106 2>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 10000>; + }; + }; + + ethernet1: ethernet1 { + status = "okay"; + st,tx-retime-src = "txclk"; + + dwmac1: dwmac@fef08000 { + status = "okay"; + phy-mode = "mii"; + snps,phy-addr = <0x1>; + + snps,reset-gpio = <&PIO4 7>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 10000>; + }; + }; + }; }; diff --git a/arch/arm/boot/dts/stih41x-b2020.dtsi b/arch/arm/boot/dts/stih41x-b2020.dtsi index 133e181..7ce1380 100644 --- a/arch/arm/boot/dts/stih41x-b2020.dtsi +++ b/arch/arm/boot/dts/stih41x-b2020.dtsi @@ -19,6 +19,7 @@ aliases { ttyAS0 = &sbc_serial1; + ethernet1 = &dwmac1; }; soc { sbc_serial1: serial@fe531000 { @@ -38,5 +39,37 @@ default-state = "off"; }; }; + + /** + * ethernet clk routing: + * for + * max-speed = <1000>; + * set + * st,tx-retime-src = "clk_125"; + * + * for + * max-speed = <100>; + * set + * st,tx-retime-src = "clkgen"; + */ + + ethernet1: ethernet1 { + status = "okay"; + st,tx-retime-src = "clkgen"; + + dwmac1: dwmac@fef08000 { + status = "okay"; + phy-mode = "rgmii-id"; + max-speed = <100>; + snps,phy-addr = <0x1>; + + snps,reset-gpio = <&PIO3 0>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 10000>; + + pinctrl-0 = <&pinctrl_rgmii1>; + }; + }; + }; };