From patchwork Mon Dec 2 16:20:04 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lorenzo Pieralisi X-Patchwork-Id: 3266091 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 9BA32C0D4A for ; Mon, 2 Dec 2013 16:20:19 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 72F7C202FF for ; Mon, 2 Dec 2013 16:20:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BFD052026F for ; Mon, 2 Dec 2013 16:20:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752799Ab3LBQUJ (ORCPT ); Mon, 2 Dec 2013 11:20:09 -0500 Received: from service87.mimecast.com ([91.220.42.44]:53791 "EHLO service87.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752800Ab3LBQUG (ORCPT ); Mon, 2 Dec 2013 11:20:06 -0500 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Mon, 02 Dec 2013 16:20:04 +0000 Received: from red-moon.cambridge.arm.com ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 2 Dec 2013 16:20:01 +0000 From: Lorenzo Pieralisi To: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, Lorenzo Pieralisi , Dave Martin , Mark Rutland , Sudeep KarkadaNagesha , Charles Garcia Tobin , Nicolas Pitre , Rob Herring , Peter De Schrijver , Grant Likely , Santosh Shilimkar , Mark Hambleton , Hanjun Guo , Daniel Lezcano , Amit Kucheria , Vincent Guittot Subject: [PATCH RFC 1/2] Documentation: arm: add cache DT bindings Date: Mon, 2 Dec 2013 16:20:04 +0000 Message-Id: <1386001205-11978-2-git-send-email-lorenzo.pieralisi@arm.com> X-Mailer: git-send-email 1.8.4 In-Reply-To: <1386001205-11978-1-git-send-email-lorenzo.pieralisi@arm.com> References: <1386001205-11978-1-git-send-email-lorenzo.pieralisi@arm.com> X-OriginalArrivalTime: 02 Dec 2013 16:20:01.0400 (UTC) FILETIME=[59EBD780:01CEEF7A] X-MC-Unique: 113120216200410401 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On ARM systems the cache topology cannot be probed at runtime, in particular, it is impossible to probe which CPUs share a given cache level. Power management software requires this knowledge to implement optimized power down sequences, hence this patch adds a document that defines the DT cache bindings for ARM systems. The bindings are compliant with ePAPR (PowerPC bindings), and rely on the cache bindings already standardized in the ePAPR v1.1 document; ARM required updates are underlined in the binding document. Signed-off-by: Lorenzo Pieralisi --- Documentation/devicetree/bindings/arm/cache.txt | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/cache.txt diff --git a/Documentation/devicetree/bindings/arm/cache.txt b/Documentation/devicetree/bindings/arm/cache.txt new file mode 100644 index 0000000..009cddb --- /dev/null +++ b/Documentation/devicetree/bindings/arm/cache.txt @@ -0,0 +1,25 @@ +========================================== +ARM processors cache binding description +========================================== + +Device tree bindings for ARM processor caches adhere to the cache bindings +described in [3], in section 3.8 for multi-level and shared caches. + +On ARM, internal caches cannot be described in the cpu node but require +specific nodes marked with compatible string set to "cache" (see [3], +section 3.8). + +Furthermore the cache bindings in [3] require the following property update: + +- [Table 3.9] cache-level: This property of cache nodes must match the cache + level encoded in the processors CLIDR (v7) and + CLIDR_EL1 (v8) registers, as described in [1][2]. + +All other properties and rules apply. + +[1] ARMv7-AR Reference Manual + http://infocenter.arm.com/help/index.jsp +[2] ARMv8-A Reference Manual + http://infocenter.arm.com/help/index.jsp +[3] ePAPR standard + https://www.power.org/documentation/epapr-version-1-1/