| Message ID | 1395121285-15383-1-git-send-email-Zhuoyu.Zhang@freescale.com (mailing list archive) |
|---|---|
| State | Accepted, archived |
| Headers | show |
On 18 March 2014 11:11, Zhuoyu Zhang <Zhuoyu.Zhang@freescale.com> wrote: > According to the data provided by HW Team, at least 12 internal platform > clock cycles are required to stabilize a DFS clock switch on FSL e500mc Socs. > This patch replaces the CPUFREQ_ETERNAL with appropriate HW clock transition > latency to make DFS governors work normally on Freescale e500mc boards. > > Signed-off-by: Zhuoyu Zhang <Zhuoyu.Zhang@freescale.com> > --- > drivers/cpufreq/ppc-corenet-cpufreq.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/drivers/cpufreq/ppc-corenet-cpufreq.c b/drivers/cpufreq/ppc-corenet-cpufreq.c > index 051000f..5977f57 100644 > --- a/drivers/cpufreq/ppc-corenet-cpufreq.c > +++ b/drivers/cpufreq/ppc-corenet-cpufreq.c > @@ -21,6 +21,7 @@ > #include <linux/of.h> > #include <linux/slab.h> > #include <linux/smp.h> > +#include <sysdev/fsl_soc.h> > > /** > * struct cpu_data - per CPU data struct > @@ -205,7 +206,8 @@ static int corenet_cpufreq_cpu_init(struct cpufreq_policy *policy) > for_each_cpu(i, per_cpu(cpu_mask, cpu)) > per_cpu(cpu_data, i) = data; > > - policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; > + policy->cpuinfo.transition_latency = > + (12 * NSEC_PER_SEC) / fsl_get_sys_freq(); > of_node_put(np); > > return 0; Acked-by: Viresh Kumar <viresh.kumar@linaro.org> -- To unsubscribe from this list: send the line "unsubscribe linux-pm" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/cpufreq/ppc-corenet-cpufreq.c b/drivers/cpufreq/ppc-corenet-cpufreq.c index 051000f..5977f57 100644 --- a/drivers/cpufreq/ppc-corenet-cpufreq.c +++ b/drivers/cpufreq/ppc-corenet-cpufreq.c @@ -21,6 +21,7 @@ #include <linux/of.h> #include <linux/slab.h> #include <linux/smp.h> +#include <sysdev/fsl_soc.h> /** * struct cpu_data - per CPU data struct @@ -205,7 +206,8 @@ static int corenet_cpufreq_cpu_init(struct cpufreq_policy *policy) for_each_cpu(i, per_cpu(cpu_mask, cpu)) per_cpu(cpu_data, i) = data; - policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; + policy->cpuinfo.transition_latency = + (12 * NSEC_PER_SEC) / fsl_get_sys_freq(); of_node_put(np); return 0;
According to the data provided by HW Team, at least 12 internal platform clock cycles are required to stabilize a DFS clock switch on FSL e500mc Socs. This patch replaces the CPUFREQ_ETERNAL with appropriate HW clock transition latency to make DFS governors work normally on Freescale e500mc boards. Signed-off-by: Zhuoyu Zhang <Zhuoyu.Zhang@freescale.com> --- drivers/cpufreq/ppc-corenet-cpufreq.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)