From patchwork Thu May 22 17:21:56 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhilash Kesavan X-Patchwork-Id: 4224961 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 4B2B3BF90B for ; Thu, 22 May 2014 17:22:29 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 280B02038F for ; Thu, 22 May 2014 17:22:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5D5EF2038D for ; Thu, 22 May 2014 17:22:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751532AbaEVRWY (ORCPT ); Thu, 22 May 2014 13:22:24 -0400 Received: from mail-pa0-f42.google.com ([209.85.220.42]:51725 "EHLO mail-pa0-f42.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751249AbaEVRWY (ORCPT ); Thu, 22 May 2014 13:22:24 -0400 Received: by mail-pa0-f42.google.com with SMTP id rd3so2798788pab.1 for ; Thu, 22 May 2014 10:22:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=w4fIZhkNmtEis8rCT9b50neysjGYTzTpJT6wuZsbzFk=; b=b65cmMbXpPWbiprLJiS9WwtZcwPbYU1fgiWgyjGyWIlqWwnASSzfw8mGO+e/29KlHF s2DdsfaG3mV0xysGO9rRQ6Vdk4E5QMmk7qTjLRj5McCaA5CXE1fd9/z513i9mF0JyKBc GwQQ+iOo8K+X2vZtY736SlKXDc3L25D120JKVBEaTL+79mzZakjcR/Ss9jO27BOFiB90 j2Fj7UMebDKPS4izRoJodHMsHW8tmfnYH2AS3P/imwwyBrwiVsgHHkLRHHVLtLnYdA9a mQARxE6oRqrmBfRj4e0LNSIj6o1li0iB4CR4rdt+LiM5hpU+tzYT97mKHzj0C03dSmIh k18w== X-Received: by 10.66.122.101 with SMTP id lr5mr69482835pab.130.1400779343571; Thu, 22 May 2014 10:22:23 -0700 (PDT) Received: from localhost.localdomain ([122.171.109.13]) by mx.google.com with ESMTPSA id cj1sm1718316pac.40.2014.05.22.10.22.20 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 22 May 2014 10:22:23 -0700 (PDT) From: Abhilash Kesavan To: linux-arm-kernel@lists.infradead.org, kgene.kim@samsung.com, t.figa@samsung.com, myungjoo.ham@samsung.com, rafael.j.wysocki@intel.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org Cc: kesavan.abhilash@gmail.com Subject: [PATCH RFC v2 1/7] clk: exynos5250: add aliases for clocks used by devfreq Date: Thu, 22 May 2014 22:51:56 +0530 Message-Id: <1400779322-4410-2-git-send-email-a.kesavan@samsung.com> X-Mailer: git-send-email 2.0.0.rc0 In-Reply-To: <1400779322-4410-1-git-send-email-a.kesavan@samsung.com> References: <1400779322-4410-1-git-send-email-a.kesavan@samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Andrew Bresticker Devfreq does not support DT-based lookup of these peripheral clocks, so add aliases for them. Signed-off-by: Andrew Bresticker Signed-off-by: Abhilash Kesavan --- drivers/clk/samsung/clk-exynos5250.c | 25 +++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 8848859..be2d7d8 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -202,6 +202,11 @@ PNAME(mout_aclk400_p) = { "mout_aclk400_g3d_mid", "mout_gpll" }; PNAME(mout_aclk200_sub_p) = { "fin_pll", "div_aclk200" }; PNAME(mout_aclk266_sub_p) = { "fin_pll", "div_aclk266" }; PNAME(mout_aclk333_sub_p) = { "fin_pll", "div_aclk333" }; +PNAME(mout_aclk300_disp1_p) = { "mout_aclk300_disp1_mid", + "mout_aclk300_disp1_mid1" }; +PNAME(mout_aclk300_gscl_p) = { "mout_aclk300_gscl_mid", + "mout_aclk300_gscl_mid1" }; +PNAME(mout_aclk300_gscl_mid1_p) = { "mout_vpll", "mout_cpll" }; PNAME(mout_hdmi_p) = { "div_hdmi_pixel", "sclk_hdmiphy" }; PNAME(mout_usb3_p) = { "mout_mpll_user", "mout_cpll" }; PNAME(mout_group1_p) = { "fin_pll", "fin_pll", "sclk_hdmi27m", @@ -278,9 +283,17 @@ static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = { */ MUX(0, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1), MUX(0, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1), + MUX(0, "mout_aclk300_disp1_mid", mout_aclk200_p, SRC_TOP0, 14, 1), + MUX(0, "mout_aclk300_disp1", mout_aclk300_disp1_p, SRC_TOP0, 15, 1), MUX(0, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1), MUX(0, "mout_aclk400_g3d_mid", mout_aclk200_p, SRC_TOP0, 20, 1), + MUX(0, "mout_aclk300_gscl_mid", mout_aclk200_p, SRC_TOP0, 24, 1), + MUX(0, "mout_aclk300_gscl", mout_aclk300_gscl_p, SRC_TOP0, 25, 2), + MUX(0, "mout_aclk300_disp1_mid1", mout_aclk300_gscl_mid1_p, + SRC_TOP1, 8, 1), + MUX(0, "mout_aclk300_gscl_mid1", mout_aclk300_gscl_mid1_p, + SRC_TOP1, 12, 1), MUX(0, "mout_aclk400_g3d", mout_aclk400_p, SRC_TOP1, 28, 1), MUX(0, "mout_cpll", mout_cpll_p, SRC_TOP2, 8, 1), @@ -357,13 +370,17 @@ static struct samsung_div_clock exynos5250_div_clks[] __initdata = { * CMU_TOP */ DIV(0, "div_aclk66", "div_aclk66_pre", DIV_TOP0, 0, 3), - DIV(0, "div_aclk166", "mout_aclk166", DIV_TOP0, 8, 3), - DIV(0, "div_aclk200", "mout_aclk200", DIV_TOP0, 12, 3), - DIV(0, "div_aclk266", "mout_mpll_user", DIV_TOP0, 16, 3), - DIV(0, "div_aclk333", "mout_aclk333", DIV_TOP0, 20, 3), + DIV_A(0, "div_aclk166", "mout_aclk166", DIV_TOP0, 8, 3, "aclk166_d"), + DIV_A(0, "div_aclk200", "mout_aclk200", DIV_TOP0, 12, 3, "aclk200_d"), + DIV_A(0, "div_aclk266", "mout_mpll_user", DIV_TOP0, 16, 3, "aclk266_d"), + DIV_A(0, "div_aclk333", "mout_aclk333", DIV_TOP0, 20, 3, "aclk333_d"), DIV(0, "div_aclk400_g3d", "mout_aclk400_g3d", DIV_TOP0, 24, 3), + DIV_A(0, "div_aclk300_disp1", "mout_aclk300_disp1", + DIV_TOP0, 28, 3, "aclk300_disp1_d"), + DIV_A(0, "div_aclk300_gscl", "mout_aclk300_gscl", + DIV_TOP1, 12, 3, "aclk300_gscl_d"), DIV(0, "div_aclk66_pre", "mout_mpll_user", DIV_TOP1, 24, 3), DIV(0, "div_cam_bayer", "mout_cam_bayer", DIV_GSCL, 12, 4),