From patchwork Fri Jun 20 06:37:40 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anson Huang X-Patchwork-Id: 4387061 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 530F29F26E for ; Fri, 20 Jun 2014 06:39:32 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6D56C203C4 for ; Fri, 20 Jun 2014 06:39:31 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 85E09203B7 for ; Fri, 20 Jun 2014 06:39:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752779AbaFTGj2 (ORCPT ); Fri, 20 Jun 2014 02:39:28 -0400 Received: from mail-bl2lp0207.outbound.protection.outlook.com ([207.46.163.207]:20477 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752765AbaFTGj2 (ORCPT ); Fri, 20 Jun 2014 02:39:28 -0400 Received: from DM2PR03CA005.namprd03.prod.outlook.com (10.141.52.153) by CY1PR0301MB0860.namprd03.prod.outlook.com (25.160.163.155) with Microsoft SMTP Server (TLS) id 15.0.959.24; Fri, 20 Jun 2014 06:39:12 +0000 Received: from BL2FFO11FD050.protection.gbl (2a01:111:f400:7c09::117) by DM2PR03CA005.outlook.office365.com (2a01:111:e400:2414::25) with Microsoft SMTP Server (TLS) id 15.0.959.24 via Frontend Transport; Fri, 20 Jun 2014 06:39:11 +0000 Received: from az84smr01.freescale.net (192.88.158.2) by BL2FFO11FD050.mail.protection.outlook.com (10.173.161.212) with Microsoft SMTP Server (TLS) id 15.0.969.12 via Frontend Transport; Fri, 20 Jun 2014 06:39:11 +0000 Received: from ubuntu.ap.freescale.net (ubuntu-010192242118.ap.freescale.net [10.192.242.118]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id s5K6d8vZ003769; Thu, 19 Jun 2014 23:39:09 -0700 From: Anson Huang To: , , Subject: [PATCH] cpufreq: imx6: remove pu regulator dependency for SOCs with no PU regulator Date: Fri, 20 Jun 2014 14:37:40 +0800 Message-ID: <1403246260-16986-1-git-send-email-b20788@freescale.com> X-Mailer: git-send-email 1.7.9.5 X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:CAL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(6009001)(199002)(189002)(105606002)(104016002)(74502001)(74662001)(50986999)(85306003)(31966008)(99396002)(95666004)(81156003)(81542001)(62966002)(26826002)(93916002)(48376002)(64706001)(19580405001)(6806004)(83322001)(77982001)(69596002)(83072002)(19580395003)(68736004)(88136002)(50226001)(79102001)(4396001)(84676001)(87286001)(85852003)(87936001)(33646001)(44976005)(104166001)(47776003)(46102001)(77156001)(50466002)(80022001)(21056001)(92566001)(2201001)(36756003)(92726001)(97736001)(102836001)(76482001)(81342001)(89996001)(20776003)(42262001); DIR:OUT; SFP:; SCL:1; SRVR:CY1PR0301MB0860; H:az84smr01.freescale.net; FPR:; MLV:ovrnspm; PTR:InfoDomainNonexistent; A:1; MX:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: BCL:0;PCL:0;RULEID: X-Forefront-PRVS: 024847EE92 Received-SPF: Fail (: domain of freescale.com does not designate 192.88.158.2 as permitted sender) receiver=; client-ip=192.88.158.2; helo=az84smr01.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=Anson.Huang@freescale.com; X-OriginatorOrg: freescale.com Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP PU regulator is not a necessary regulator for cpufreq, not all i.MX6 SoCs have PU regulator, only if SOC has PU regulator, then its voltage must be equal to SOC regulator, so remove the dependency to support i.MX6SX which has no PU regulator. Signed-off-by: Anson Huang --- drivers/cpufreq/imx6q-cpufreq.c | 33 ++++++++++++++++++++------------- 1 file changed, 20 insertions(+), 13 deletions(-) diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c index af366c2..384a63d 100644 --- a/drivers/cpufreq/imx6q-cpufreq.c +++ b/drivers/cpufreq/imx6q-cpufreq.c @@ -66,10 +66,12 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) /* scaling up? scale voltage before frequency */ if (new_freq > old_freq) { - ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0); - if (ret) { - dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret); - return ret; + if (!IS_ERR(pu_reg)) { + ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0); + if (ret) { + dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret); + return ret; + } } ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0); if (ret) { @@ -121,10 +123,12 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index) dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret); ret = 0; } - ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0); - if (ret) { - dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret); - ret = 0; + if (!IS_ERR(pu_reg)) { + ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0); + if (ret) { + dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret); + ret = 0; + } } } @@ -184,7 +188,7 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev) arm_reg = regulator_get(cpu_dev, "arm"); pu_reg = regulator_get(cpu_dev, "pu"); soc_reg = regulator_get(cpu_dev, "soc"); - if (IS_ERR(arm_reg) || IS_ERR(pu_reg) || IS_ERR(soc_reg)) { + if (IS_ERR(arm_reg) || IS_ERR(soc_reg)) { dev_err(cpu_dev, "failed to get regulators\n"); ret = -ENOENT; goto put_reg; @@ -268,9 +272,11 @@ soc_opp_out: ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]); if (ret > 0) transition_latency += ret * 1000; - ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]); - if (ret > 0) - transition_latency += ret * 1000; + if (!IS_ERR(pu_reg)) { + ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]); + if (ret > 0) + transition_latency += ret * 1000; + } /* * OPP is maintained in order of increasing frequency, and @@ -327,7 +333,8 @@ static int imx6q_cpufreq_remove(struct platform_device *pdev) cpufreq_unregister_driver(&imx6q_cpufreq_driver); dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table); regulator_put(arm_reg); - regulator_put(pu_reg); + if (!IS_ERR(pu_reg)) + regulator_put(pu_reg); regulator_put(soc_reg); clk_put(arm_clk); clk_put(pll1_sys_clk);