From patchwork Fri Jun 27 13:22:52 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 4435031 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 3F2C4BEECB for ; Fri, 27 Jun 2014 13:24:07 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6FD9F20381 for ; Fri, 27 Jun 2014 13:24:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 7D9872038F for ; Fri, 27 Jun 2014 13:24:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753466AbaF0NYD (ORCPT ); Fri, 27 Jun 2014 09:24:03 -0400 Received: from top.free-electrons.com ([176.31.233.9]:42123 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753292AbaF0NYB (ORCPT ); Fri, 27 Jun 2014 09:24:01 -0400 Received: by mail.free-electrons.com (Postfix, from userid 106) id 8C457994; Fri, 27 Jun 2014 15:24:01 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from localhost (tra42-5-83-152-246-54.fbx.proxad.net [83.152.246.54]) by mail.free-electrons.com (Postfix) with ESMTPSA id 0F0AA924; Fri, 27 Jun 2014 15:24:01 +0200 (CEST) From: Gregory CLEMENT To: Daniel Lezcano , "Rafael J. Wysocki" , linux-pm@vger.kernel.org, Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Gregory CLEMENT Cc: Thomas Petazzoni , Ezequiel Garcia , linux-arm-kernel@lists.infradead.org, Lior Amsalem , Tawfik Bayouk , Nadav Haklai , devicetree@vger.kernel.org Subject: [PATCH 11/16] ARM: mvebu: dts: Add CA9 MPcore SoC Controller node Date: Fri, 27 Jun 2014 15:22:52 +0200 Message-Id: <1403875377-940-12-git-send-email-gregory.clement@free-electrons.com> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1403875377-940-1-git-send-email-gregory.clement@free-electrons.com> References: <1403875377-940-1-git-send-email-gregory.clement@free-electrons.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The CA9 MPcore SoC Control block allows to do some configuration that the SoC could use for a specific use case. In most cases the defaults case is enough. However there is few exception: for cpuidle we need to use the CA9 MPcore Reset Control register. The documentation is also updated in the same time. Signed-off-by: Gregory CLEMENT Cc: devicetree@vger.kernel.org Reviewed-by: Thomas Petazzoni --- .../devicetree/bindings/arm/armada-380-mpcore-soc-ctrl.txt | 14 ++++++++++++++ arch/arm/boot/dts/armada-38x.dtsi | 5 +++++ 2 files changed, 19 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/armada-380-mpcore-soc-ctrl.txt diff --git a/Documentation/devicetree/bindings/arm/armada-380-mpcore-soc-ctrl.txt b/Documentation/devicetree/bindings/arm/armada-380-mpcore-soc-ctrl.txt new file mode 100644 index 000000000000..0a2df51ba560 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/armada-380-mpcore-soc-ctrl.txt @@ -0,0 +1,14 @@ +Marvell Armada 38x CA9 MPcore SoC Controller +============================================ + +Required properties: + +- compatible: Should be "marvell,armada-380-mpcore-soc-ctrl". + +- reg: should be register base and length as documented in the + datasheet for the CA9 MPcore SoC Control registers + +mpcore-soc-ctrl@20d20 { + compatible = "marvell,armada-380-mpcore-soc-ctrl"; + reg = <0x20d20 0x6c>; +}; diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 689fa1a46728..242d0ecc99f3 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -286,6 +286,11 @@ reg = <0x20800 0x10>; }; + mpcore-soc-ctrl@20d20 { + compatible = "marvell,armada-380-mpcore-soc-ctrl"; + reg = <0x20d20 0x6c>; + }; + coherency-fabric@21010 { compatible = "marvell,armada-380-coherency-fabric"; reg = <0x21010 0x1c>;