From patchwork Fri Jun 27 13:22:46 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 4434971 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id B35C59F383 for ; Fri, 27 Jun 2014 13:23:58 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DAE0B2026D for ; Fri, 27 Jun 2014 13:23:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 03D53203A9 for ; Fri, 27 Jun 2014 13:23:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753189AbaF0NXz (ORCPT ); Fri, 27 Jun 2014 09:23:55 -0400 Received: from top.free-electrons.com ([176.31.233.9]:42073 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753157AbaF0NXz (ORCPT ); Fri, 27 Jun 2014 09:23:55 -0400 Received: by mail.free-electrons.com (Postfix, from userid 106) id B28AF914; Fri, 27 Jun 2014 15:23:54 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from localhost (tra42-5-83-152-246-54.fbx.proxad.net [83.152.246.54]) by mail.free-electrons.com (Postfix) with ESMTPSA id 38FE67EC; Fri, 27 Jun 2014 15:23:54 +0200 (CEST) From: Gregory CLEMENT To: Daniel Lezcano , "Rafael J. Wysocki" , linux-pm@vger.kernel.org, Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Gregory CLEMENT Cc: Thomas Petazzoni , Ezequiel Garcia , linux-arm-kernel@lists.infradead.org, Lior Amsalem , Tawfik Bayouk , Nadav Haklai Subject: [PATCH 05/16] ARM: mvebu: Add workaround for cpuidle support for Armada 370 Date: Fri, 27 Jun 2014 15:22:46 +0200 Message-Id: <1403875377-940-6-git-send-email-gregory.clement@free-electrons.com> X-Mailer: git-send-email 1.8.1.2 In-Reply-To: <1403875377-940-1-git-send-email-gregory.clement@free-electrons.com> References: <1403875377-940-1-git-send-email-gregory.clement@free-electrons.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Armada 370, there is "a slow exit process from the deep idle state due to heavy L1/L2 cache cleanup operations performed by the BootROM software" (cf errata GL-BootROM-10). To avoid this, we replace the restart code of the BootROM by a simple jump to the boot address. Then the code located at this boot address will take care of the initialization. For this purpose, we use the common function mvebu_boot_addr_wa() introduced in the previous commit. Signed-off-by: Gregory CLEMENT --- arch/arm/mach-mvebu/pmsu.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c index 991560905ccc..cdc6d87d0b49 100644 --- a/arch/arm/mach-mvebu/pmsu.c +++ b/arch/arm/mach-mvebu/pmsu.c @@ -34,7 +34,6 @@ #include #include "common.h" -static void __iomem *pmsu_mp_base; #define PMSU_BASE_OFFSET 0x100 #define PMSU_REG_SIZE 0x1000 @@ -77,6 +76,9 @@ extern void ll_enable_coherency(void); extern void armada_370_xp_cpu_resume(void); +static unsigned long pmsu_mp_phys_base; +static void __iomem *pmsu_mp_base; + static struct platform_device armada_xp_cpuidle_device = { .name = "cpuidle-armada-370-xp", }; @@ -147,6 +149,8 @@ static int __init armada_370_xp_pmsu_init(void) goto out; } + pmsu_mp_phys_base = res.start; + pmsu_mp_base = ioremap(res.start, resource_size(&res)); if (!pmsu_mp_base) { pr_err("unable to map registers\n"); @@ -312,6 +316,18 @@ int __init armada_370_xp_cpu_pm_init(void) return 0; of_node_put(np); + /* + * On Armada 370, there is "a slow exit process from the deep + * idle state due to heavy L1/L2 cache cleanup operations + * performed by the BootROM software". To avoid this, we + * replace the restart code of the bootrom by a a simple jump + * to the boot address. Then the code located at this boot + * address will take care of the initialization. + */ + if (of_machine_is_compatible("marvell,armada370")) + mvebu_boot_addr_wa(ARMADA_370_CRYPT0_ENG_ID, pmsu_mp_phys_base + + PMSU_BOOT_ADDR_REDIRECT_OFFSET(0)); + armada_370_xp_pmsu_enable_l2_powerdown_onidle(); armada_xp_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend; platform_device_register(&armada_xp_cpuidle_device);