From patchwork Tue Jul 15 18:33:42 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abhilash Kesavan X-Patchwork-Id: 4557091 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id D9F679F37C for ; Tue, 15 Jul 2014 18:34:15 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D235E20179 for ; Tue, 15 Jul 2014 18:34:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id CE7B620158 for ; Tue, 15 Jul 2014 18:34:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932788AbaGOSeM (ORCPT ); Tue, 15 Jul 2014 14:34:12 -0400 Received: from mail-pa0-f50.google.com ([209.85.220.50]:33875 "EHLO mail-pa0-f50.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932786AbaGOSeM (ORCPT ); Tue, 15 Jul 2014 14:34:12 -0400 Received: by mail-pa0-f50.google.com with SMTP id et14so2293506pad.37 for ; Tue, 15 Jul 2014 11:34:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=f68uh2wKHZyX3pRcaQlzdce/XJfKePgzuFs0abqgje0=; b=UFX5C8JxXDClqCFFXVzMnQaXeNrSBz7Yf2lzsXnc9UZ5jAxHXtFTx/avv097S+ogCz RtvaP6NMswBLi8Pk8BSEPW2lhDc7+/OgaHKIQs7/kj30w4B4RmFc2n65Um7xpOmMGM+E AbMdsCdK45DiElgLkfYnuYM8ecH5lnWgpHW4v9RTIMPaIMAIme9w8Av/w64+gTPTA5Ob IUqS7YkwThW94P85x93axekib5A4D+Q8moxqTBvzZ0ojNze/oNu+nrfCvRjlusLemQaB AegUzh4otCu+ERbAldSm3jQ8F6zkah/AumxLa5NFay/BS8jB+FWsFVpQ6Ab3r0oXD7QK l3KA== X-Received: by 10.66.139.131 with SMTP id qy3mr5361404pab.130.1405449251353; Tue, 15 Jul 2014 11:34:11 -0700 (PDT) Received: from localhost.localdomain ([122.167.175.14]) by mx.google.com with ESMTPSA id fn1sm3481048pbc.77.2014.07.15.11.33.57 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 15 Jul 2014 11:34:00 -0700 (PDT) From: Abhilash Kesavan To: myungjoo.ham@samsung.com, linux-pm@vger.kernel.org, kgene.kim@samsung.com Cc: rjw@sisk.pl, t.figa@samsung.com, kesavan.abhilash@gmail.com, devicetree@vger.kernel.org Subject: [PATCH v3 1/7] clk: exynos5250: add aliases for clocks used by devfreq Date: Wed, 16 Jul 2014 00:03:42 +0530 Message-Id: <1405449222-26186-1-git-send-email-a.kesavan@samsung.com> X-Mailer: git-send-email 2.0.1 In-Reply-To: <1400779322-4410-2-git-send-email-a.kesavan@samsung.com> References: <1400779322-4410-2-git-send-email-a.kesavan@samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-6.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Andrew Bresticker Devfreq does not support DT-based lookup of these peripheral clocks, so add aliases for them. Signed-off-by: Andrew Bresticker Signed-off-by: Abhilash Kesavan --- drivers/clk/samsung/clk-exynos5250.c | 25 +++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index 184f642..48a2264 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -226,6 +226,11 @@ PNAME(mout_aclk200_p) = { "mout_mpll_user", "mout_bpll_user" }; PNAME(mout_aclk400_p) = { "mout_aclk400_g3d_mid", "mout_gpll" }; PNAME(mout_aclk200_sub_p) = { "fin_pll", "div_aclk200" }; PNAME(mout_aclk266_sub_p) = { "fin_pll", "div_aclk266" }; +PNAME(mout_aclk300_disp1_p) = { "mout_aclk300_disp1_mid", + "mout_aclk300_disp1_mid1" }; +PNAME(mout_aclk300_gscl_p) = { "mout_aclk300_gscl_mid", + "mout_aclk300_gscl_mid1" }; +PNAME(mout_aclk300_gscl_mid1_p) = { "mout_vpll", "mout_cpll" }; PNAME(mout_aclk333_sub_p) = { "fin_pll", "div_aclk333" }; PNAME(mout_aclk400_isp_sub_p) = { "fin_pll", "div_aclk400_isp" }; PNAME(mout_hdmi_p) = { "div_hdmi_pixel", "sclk_hdmiphy" }; @@ -304,9 +309,17 @@ static struct samsung_mux_clock exynos5250_mux_clks[] __initdata = { */ MUX(0, "mout_aclk166", mout_aclk166_p, SRC_TOP0, 8, 1), MUX(0, "mout_aclk200", mout_aclk200_p, SRC_TOP0, 12, 1), + MUX(0, "mout_aclk300_disp1_mid", mout_aclk200_p, SRC_TOP0, 14, 1), + MUX(0, "mout_aclk300_disp1", mout_aclk300_disp1_p, SRC_TOP0, 15, 1), MUX(0, "mout_aclk333", mout_aclk166_p, SRC_TOP0, 16, 1), MUX(0, "mout_aclk400_g3d_mid", mout_aclk200_p, SRC_TOP0, 20, 1), + MUX(0, "mout_aclk300_gscl_mid", mout_aclk200_p, SRC_TOP0, 24, 1), + MUX(0, "mout_aclk300_gscl", mout_aclk300_gscl_p, SRC_TOP0, 25, 2), + MUX(0, "mout_aclk300_disp1_mid1", mout_aclk300_gscl_mid1_p, + SRC_TOP1, 8, 1), + MUX(0, "mout_aclk300_gscl_mid1", mout_aclk300_gscl_mid1_p, + SRC_TOP1, 12, 1), MUX(0, "mout_aclk400_isp", mout_aclk200_p, SRC_TOP1, 24, 1), MUX(0, "mout_aclk400_g3d", mout_aclk400_p, SRC_TOP1, 28, 1), @@ -387,13 +400,17 @@ static struct samsung_div_clock exynos5250_div_clks[] __initdata = { * CMU_TOP */ DIV(0, "div_aclk66", "div_aclk66_pre", DIV_TOP0, 0, 3), - DIV(0, "div_aclk166", "mout_aclk166", DIV_TOP0, 8, 3), - DIV(0, "div_aclk200", "mout_aclk200", DIV_TOP0, 12, 3), - DIV(0, "div_aclk266", "mout_mpll_user", DIV_TOP0, 16, 3), - DIV(0, "div_aclk333", "mout_aclk333", DIV_TOP0, 20, 3), + DIV_A(0, "div_aclk166", "mout_aclk166", DIV_TOP0, 8, 3, "aclk166_d"), + DIV_A(0, "div_aclk200", "mout_aclk200", DIV_TOP0, 12, 3, "aclk200_d"), + DIV_A(0, "div_aclk266", "mout_mpll_user", DIV_TOP0, 16, 3, "aclk266_d"), + DIV_A(0, "div_aclk333", "mout_aclk333", DIV_TOP0, 20, 3, "aclk333_d"), DIV(0, "div_aclk400_g3d", "mout_aclk400_g3d", DIV_TOP0, 24, 3), + DIV_A(0, "div_aclk300_disp1", "mout_aclk300_disp1", + DIV_TOP0, 28, 3, "aclk300_disp1_d"), + DIV_A(0, "div_aclk300_gscl", "mout_aclk300_gscl", + DIV_TOP1, 12, 3, "aclk300_gscl_d"), DIV(0, "div_aclk400_isp", "mout_aclk400_isp", DIV_TOP1, 20, 3), DIV(0, "div_aclk66_pre", "mout_mpll_user", DIV_TOP1, 24, 3),