From patchwork Tue Aug 19 03:33:19 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tuomas Tynkkynen X-Patchwork-Id: 4740361 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 05175C0338 for ; Tue, 19 Aug 2014 03:44:00 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 294DA20131 for ; Tue, 19 Aug 2014 03:43:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4C29120123 for ; Tue, 19 Aug 2014 03:43:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751880AbaHSDnj (ORCPT ); Mon, 18 Aug 2014 23:43:39 -0400 Received: from script.cs.helsinki.fi ([128.214.11.1]:35842 "EHLO script.cs.helsinki.fi" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752553AbaHSDjl (ORCPT ); Mon, 18 Aug 2014 23:39:41 -0400 X-Greylist: delayed 328 seconds by postgrey-1.27 at vger.kernel.org; Mon, 18 Aug 2014 23:39:37 EDT X-DKIM: Courier DKIM Filter v0.50+pk-2014-03-23 mail.cs.helsinki.fi Tue, 19 Aug 2014 06:34:10 +0300 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cs.helsinki.fi; h=from:to:cc:subject:date:message-id:in-reply-to:references; s= dkim20130528; bh=mOMFzexD5H534wkQVcljuMsQFzrEqBkXazY5A3TdzjA=; b= OrBzhnOGdHHuyJXtRyCDo1CjNDxZlgY7vh/9cwdRPkkE9Sz//GfP+MUhb6X3OU5W mze+/JOArtPrG/ym5Dy1O9q3LUly0zdcjP8d1Ffcg7udmJYCnnzJAUxHfYnsP3zd 7aUBVuAYK3PSZhwvBoCkJp9iYnGcZfayRlSscAoE1z0= Received: from melkki.cs.helsinki.fi (melkki.cs.helsinki.fi [128.214.9.98]) (AUTH: PLAIN cs-relay, TLS: TLSv1/SSLv3,256bits,AES256-SHA) by mail.cs.helsinki.fi with ESMTPSA; Tue, 19 Aug 2014 06:34:10 +0300 id 0000000000080D92.0000000053F2C5B2.0000566D Received: by melkki.cs.helsinki.fi (Postfix, from userid 18244) id BE9491C9634; Tue, 19 Aug 2014 06:34:04 +0300 (EEST) From: Tuomas Tynkkynen To: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org Cc: Stephen Warren , Thierry Reding , Peter De Schrijver , Prashant Gaikwad , Mike Turquette , "Rafael J. Wysocki" , Viresh Kumar , Paul Walmsley , Vince Hsu , devicetree@vger.kernel.org, Tuomas Tynkkynen Subject: [PATCH v3 09/15] ARM: tegra: Add the DFLL to Tegra124 device tree Date: Tue, 19 Aug 2014 06:33:19 +0300 Message-Id: <1408419205-10048-10-git-send-email-tuomas.tynkkynen@iki.fi> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1408419205-10048-1-git-send-email-tuomas.tynkkynen@iki.fi> References: <1408419205-10048-1-git-send-email-tuomas.tynkkynen@iki.fi> X-NVConfidentiality: public Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Tuomas Tynkkynen The DFLL clocksource is a separate IP block from the usual clock-and-reset controller, so it gets its own device tree node. Signed-off-by: Tuomas Tynkkynen --- arch/arm/boot/dts/tegra124.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 03916ef..8ff4332 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -544,6 +544,28 @@ status = "disabled"; }; + dfll: dfll@0,70110000 { + compatible = "nvidia,tegra124-dfll"; + reg = <0 0x70110000 0 0x100>, /* DFLL control */ + <0 0x70110000 0 0x100>, /* I2C output control */ + <0 0x70110100 0 0x100>, /* Integrated I2C controller */ + <0 0x70110200 0 0x100>; /* Look-up table RAM */ + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>, + <&tegra_car TEGRA124_CLK_DFLL_REF>, + <&tegra_car TEGRA124_CLK_I2C5>; + clock-names = "soc", "ref", "i2c"; + #clock-cells = <0>; + clock-output-names = "dfllCPU_out"; + nvidia,sample-rate = <12500>; + nvidia,droop-ctrl = <0x00000f00>; + nvidia,force-mode = <1>; + nvidia,cf = <10>; + nvidia,ci = <0>; + nvidia,cg = <2>; + status = "disabled"; + }; + ahub@0,70300000 { compatible = "nvidia,tegra124-ahub"; reg = <0x0 0x70300000 0x0 0x200>,