From patchwork Mon Nov 3 03:53:09 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kachhap X-Patchwork-Id: 5213851 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 9A074C11AC for ; Mon, 3 Nov 2014 04:04:26 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A0BF2201E4 for ; Mon, 3 Nov 2014 04:04:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8AD1420204 for ; Mon, 3 Nov 2014 04:04:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752028AbaKCEEV (ORCPT ); Sun, 2 Nov 2014 23:04:21 -0500 Received: from mailout4.samsung.com ([203.254.224.34]:18640 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751739AbaKCEEU (ORCPT ); Sun, 2 Nov 2014 23:04:20 -0500 Received: from epcpsbgr5.samsung.com (u145.gpu120.samsung.co.kr [203.254.230.145]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0NEG00L5H3B79730@mailout4.samsung.com>; Mon, 03 Nov 2014 13:04:19 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.124]) by epcpsbgr5.samsung.com (EPCPMTA) with SMTP id DF.3D.19034.3CEF6545; Mon, 03 Nov 2014 13:04:19 +0900 (KST) X-AuditID: cbfee691-f79b86d000004a5a-3c-5456fec3ab3d Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 92.2A.09430.3CEF6545; Mon, 03 Nov 2014 13:04:19 +0900 (KST) Received: from chromebld-server.sisodomain.com ([107.108.73.106]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0NEG00BUJ320LR40@mmp2.samsung.com>; Mon, 03 Nov 2014 13:04:19 +0900 (KST) From: Amit Daniel Kachhap To: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-pm@vger.kernel.org Cc: kgene.kim@samsung.com, pankaj.dubey@samsung.com, Amit Daniel Kachhap , Sylwester Nawrocki , Mike Turquette Subject: [PATCH 11/12] clk: samsung: save and restore clock registers for power domain Date: Mon, 03 Nov 2014 09:23:09 +0530 Message-id: <1414986790-11940-12-git-send-email-amit.daniel@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1414986790-11940-1-git-send-email-amit.daniel@samsung.com> References: <1414986790-11940-1-git-send-email-amit.daniel@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrBLMWRmVeSWpSXmKPExsWyRsSkRvfwv7AQg237hC0aroZY9C64ymax 6fE1VovPvUcYLWac38dk8XTCRTaLRVu/sFscftPO6sDhcefaHjaPzUvqPfq2rGL0+LxJLoAl issmJTUnsyy1SN8ugStj1fJHzAWzlSsOHDvP1sC4UraLkYNDQsBE4vqJ2i5GTiBTTOLCvfVs XYxcHEICSxkl1j1bxgqRMJH4eWsSK0RiOqNE1/FtTBDOBCaJWWdeg1WxCRhL/Ny5nx3EFhFI l1izaDfYKGaBvYwSi4/eZwFJCAtESOxsaGICsVkEVCW+7njCBnIGr4CHxJOtkRAXKUjMmWQD UsEJFD3Zdx1svJCAu8Skd8/B9koITGeXmDttBQvEGAGJb5MPsUD0ykpsOsAMcbSkxMEVN1gm MAovYGRYxSiaWpBcUJyUXmSqV5yYW1yal66XnJ+7iREY4Kf/PZu4g/H+AetDjAIcjEo8vAXb w0KEWBPLiitzDzGaAm2YyCwlmpwPjKO8knhDYzMjC1MTU2Mjc0szJXFeHemfwUIC6Yklqdmp qQWpRfFFpTmpxYcYmTg4pRoYC0oYX03ceCn3dX/5PtM8Q3/Z3x/7zbVt/+876LRORZsnfK9s 5mO5dgkFlRNiQRV11eIWNx8rfxIt1DkhGrHj22SPqzs0D/DvXvaC6fffWTltc5376g+8zc5u 85fq8cxNf9bT/fzoOyF+Y6PZx7Ztbtu4ct6FiCkyey9I5Xxe88+l/JdN1wp/JZbijERDLeai 4kQAhZkI0GsCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrMIsWRmVeSWpSXmKPExsVy+t9jQd3D/8JCDL5+57JouBpi0bvgKpvF psfXWC0+9x5htJhxfh+TxdMJF9ksFm39wm5x+E07qwOHx51re9g8Ni+p9+jbsorR4/MmuQCW qAZGm4zUxJTUIoXUvOT8lMy8dFsl7+B453hTMwNDXUNLC3MlhbzE3FRbJRefAF23zBygK5QU yhJzSoFCAYnFxUr6dpgmhIa46VrANEbo+oYEwfUYGaCBhDWMGauWP2IumK1cceDYebYGxpWy XYycHBICJhI/b01ihbDFJC7cW8/WxcjFISQwnVGi6/g2JghnApPErDOvwarYBIwlfu7czw5i iwikS6xZtBusg1lgL6PE4qP3WUASwgIREjsbmphAbBYBVYmvO54AFXFw8Ap4SDzZGgliSggo SMyZZANSwQkUPdl3HWy8kIC7xKR3z5kmMPIuYGRYxSiaWpBcUJyUnmukV5yYW1yal66XnJ+7 iREcQc+kdzCuarA4xCjAwajEw1uwPSxEiDWxrLgy9xCjBAezkghv5VqgEG9KYmVValF+fFFp TmrxIUZToJsmMkuJJucDozuvJN7Q2MTc1NjU0sTCxMxSSZz3YKt1oJBAemJJanZqakFqEUwf EwenVAOjXd0FHd7AvWcPiq32cmeaOmEK70mHugO3Zu9qL5nKJzI7NXJniqT2MqY5yqYXp5eI Gn+29v566GXESpeCw/JP4ztePtgZG8Yy348zpGyJXuXXVzpnXk3WWxOcmaZ3y3eNscoctviN gd/+PVhkfXKWe3WW6omVR7XShU21IgLWLJDpSXCc1rxUiaU4I9FQi7moOBEAgITk7LYCAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds support for save and restore for clock registers which loses register contents across power domain off/on sequence. Cc: Sylwester Nawrocki Cc: Mike Turquette Reviewed-by: Pankaj Dubey Signed-off-by: Amit Daniel Kachhap --- drivers/clk/samsung/clk.c | 66 +++++++++++++++++++++++++++++++++++++++++++++ drivers/clk/samsung/clk.h | 14 ++++++++++ 2 files changed, 80 insertions(+) diff --git a/drivers/clk/samsung/clk.c b/drivers/clk/samsung/clk.c index dd1f7c9..9fd1369 100644 --- a/drivers/clk/samsung/clk.c +++ b/drivers/clk/samsung/clk.c @@ -11,10 +11,12 @@ * clock framework for Samsung platforms. */ +#include #include #include "clk.h" static LIST_HEAD(clock_reg_cache_list); +static LIST_HEAD(clock_pd_reg_cache_list); void samsung_clk_save(void __iomem *base, struct samsung_clk_reg_dump *rd, @@ -370,6 +372,67 @@ static void samsung_clk_sleep_init(void __iomem *reg_base, unsigned long nr_rdump) {} #endif +static int samsung_power_domain_notifier(struct notifier_block *nb, + unsigned long event, void *data) +{ + struct generic_pm_domain *genpd = data; + struct samsung_clock_pd_reg_cache *reg_cache; + + switch (event) { + case GPD_OFF_PRE: + /* save all the pd domain clock registers */ + list_for_each_entry(reg_cache, &clock_pd_reg_cache_list, node) + if (!strcmp(reg_cache->pd_name, genpd->name)) + samsung_clk_save(reg_cache->reg_base, + reg_cache->rdump, + reg_cache->rd_num); + break; + case GPD_ON_POST: + /* restore all the pd domain clock registers */ + list_for_each_entry(reg_cache, &clock_pd_reg_cache_list, node) + if (!strcmp(reg_cache->pd_name, genpd->name)) + samsung_clk_restore(reg_cache->reg_base, + reg_cache->rdump, + reg_cache->rd_num); + break; + case GPD_OFF_POST: + case GPD_ON_PRE: + break; + default: + pr_err("%s: Invalid pm domain event\n", __func__); + } + return 0; +} + +/* Notifier for power domain on/off changes */ +static struct notifier_block power_domain_notifier_block = { + .notifier_call = samsung_power_domain_notifier, +}; + +static void samsung_clk_pd_init(void __iomem *reg_base, + const unsigned long *rdump, unsigned long nr_rdump, + char *pd_name) +{ + struct samsung_clock_pd_reg_cache *pd_reg_cache; + + pd_reg_cache = kzalloc(sizeof(struct samsung_clock_pd_reg_cache), + GFP_KERNEL); + if (!pd_reg_cache) + panic("could not allocate register reg_cache.\n"); + + pd_reg_cache->rdump = samsung_clk_alloc_reg_dump(rdump, nr_rdump); + + if (!pd_reg_cache->rdump) + panic("could not allocate register dump storage.\n"); + + pd_reg_cache->reg_base = reg_base; + pd_reg_cache->rd_num = nr_rdump; + pd_reg_cache->pd_name = pd_name; + list_add_tail(&pd_reg_cache->node, &clock_pd_reg_cache_list); + + genpd_register_notifier(&power_domain_notifier_block, pd_name); +} + /* * Common function which registers plls, muxes, dividers and gates * for each CMU. It also add CMU register list to register cache. @@ -408,6 +471,9 @@ void __init samsung_cmu_register_one(struct device_node *np, if (cmu->clk_regs) samsung_clk_sleep_init(reg_base, cmu->clk_regs, cmu->nr_clk_regs); + if (cmu->pd_clk_regs) + samsung_clk_pd_init(reg_base, cmu->pd_clk_regs, + cmu->nr_clk_regs, cmu->pd_name); samsung_clk_of_add_provider(np, ctx); } diff --git a/drivers/clk/samsung/clk.h b/drivers/clk/samsung/clk.h index 3f471e9..f67f5e5 100644 --- a/drivers/clk/samsung/clk.h +++ b/drivers/clk/samsung/clk.h @@ -331,6 +331,14 @@ struct samsung_clock_reg_cache { unsigned int rd_num; }; +struct samsung_clock_pd_reg_cache { + struct list_head node; + void __iomem *reg_base; + struct samsung_clk_reg_dump *rdump; + unsigned int rd_num; + char *pd_name; +}; + struct samsung_cmu_info { /* list of pll clocks and respective count */ struct samsung_pll_clock *pll_clks; @@ -356,6 +364,12 @@ struct samsung_cmu_info { /* list and number of clocks registers */ unsigned long *clk_regs; unsigned int nr_clk_regs; + + /* list and number of clocks to be saved/restored during + * power domain shutdown */ + char *pd_name; + unsigned long *pd_clk_regs; + unsigned int nr_pd_clk_regs; }; extern struct samsung_clk_provider *__init samsung_clk_init(