From patchwork Mon Nov 3 03:53:03 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Amit Kachhap X-Patchwork-Id: 5213691 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id D4CB6C11AD for ; Mon, 3 Nov 2014 04:02:17 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id CD54B20256 for ; Mon, 3 Nov 2014 04:02:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6275D20253 for ; Mon, 3 Nov 2014 04:02:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752537AbaKCECM (ORCPT ); Sun, 2 Nov 2014 23:02:12 -0500 Received: from mailout1.samsung.com ([203.254.224.24]:61016 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752392AbaKCECL (ORCPT ); Sun, 2 Nov 2014 23:02:11 -0500 Received: from epcpsbgr1.samsung.com (u141.gpu120.samsung.co.kr [203.254.230.141]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0NEG00FIJ37LD1C0@mailout1.samsung.com>; Mon, 03 Nov 2014 13:02:09 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [172.20.52.126]) by epcpsbgr1.samsung.com (EPCPMTA) with SMTP id 73.3B.17016.14EF6545; Mon, 03 Nov 2014 13:02:09 +0900 (KST) X-AuditID: cbfee68d-f79296d000004278-a1-5456fe414c63 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 28.A9.09430.14EF6545; Mon, 03 Nov 2014 13:02:09 +0900 (KST) Received: from chromebld-server.sisodomain.com ([107.108.73.106]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0NEG00BUJ320LR40@mmp2.samsung.com>; Mon, 03 Nov 2014 13:02:08 +0900 (KST) From: Amit Daniel Kachhap To: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-pm@vger.kernel.org Cc: kgene.kim@samsung.com, pankaj.dubey@samsung.com, Amit Daniel Kachhap Subject: [PATCH 05/12] arm: exynos: Add platform driver support for power domain driver Date: Mon, 03 Nov 2014 09:23:03 +0530 Message-id: <1414986790-11940-6-git-send-email-amit.daniel@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1414986790-11940-1-git-send-email-amit.daniel@samsung.com> References: <1414986790-11940-1-git-send-email-amit.daniel@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrFLMWRmVeSWpSXmKPExsWyRsSkTtfxX1iIwcF1ShYNV0MsehdcZbPY 9Pgaq8Xn3iOMFjPO72OyWLT1C7sDm8fmJfUefVtWMXp83iQXwBzFZZOSmpNZllqkb5fAlXF+ /kz2giNaFR+2bGVvYDys1MXIySEhYCKx7s1LVghbTOLCvfVsXYxcHEICSxkl3jxvZIYp6v4z nREiMZ1RYvK8b0wQzgQmiY0Lt7CBVLEJGEv83LmfHcQWEUiXWLNoN1icWSBF4vL0DiYQW1gg UuL9muVgcRYBVYmTe/rB6nkF3CU+fLrM0sXIAbRNQWLOJBuQMKeAh8TJvutg1wkBlUx69xxs r4TAfzaJF1taGSHmCEh8m3wIqldWYtMBqKMlJQ6uuMEygVF4ASPDKkbR1ILkguKk9CJDveLE 3OLSvHS95PzcTYzAID7971nvDsbbB6wPMQpwMCrx8BZsDwsRYk0sK67MPcRoCrRhIrOUaHI+ MFbySuINjc2MLExNTI2NzC3NlMR5FaV+BgsJpCeWpGanphakFsUXleakFh9iZOLglGpglAu7 Uhy9/L7A7cWbuv8+b79X8Fp9+gKJt9MV3/vYbvr/s85KwNT8d5G1M3dg0T2z0IXRhxrvi9ju e7SL+ZKqSFh984PzXx29jSZyFXbGJyx9M8V+/u3p3A3bIntnZ/dkunYLZDxXfeWc8GBX81Lb m/eiclZO2N4UX6D0oupmbr2NUbaM9g9LJZbijERDLeai4kQAWPcGcl0CAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprCIsWRmVeSWpSXmKPExsVy+t9jQV3Hf2EhBn9fSlk0XA2x6F1wlc1i 0+NrrBafe48wWsw4v4/JYtHWL+wObB6bl9R79G1ZxejxeZNcAHNUA6NNRmpiSmqRQmpecn5K Zl66rZJ3cLxzvKmZgaGuoaWFuZJCXmJuqq2Si0+ArltmDtBaJYWyxJxSoFBAYnGxkr4dpgmh IW66FjCNEbq+IUFwPUYGaCBhDWPG+fkz2QuOaFV82LKVvYHxsFIXIyeHhICJRPef6YwQtpjE hXvr2boYuTiEBKYzSkye940JwpnAJLFx4RY2kCo2AWOJnzv3s4PYIgLpEmsW7QaLMwukSFye 3sEEYgsLREq8X7McLM4ioCpxck8/WD2vgLvEh0+XWboYOYC2KUjMmWQDEuYU8JA42XedFcQW AiqZ9O450wRG3gWMDKsYRVMLkguKk9JzjfSKE3OLS/PS9ZLzczcxgmPkmfQOxlUNFocYBTgY lXh4C7aHhQixJpYVV+YeYpTgYFYS4a1cCxTiTUmsrEotyo8vKs1JLT7EaAp01ERmKdHkfGD8 5pXEGxqbmJsam1qaWJiYWSqJ8x5stQ4UEkhPLEnNTk0tSC2C6WPi4JRqYFTgWBthW7J83abF Z2x7Dc9d6JDjKDnyYIp6RXrh7wCJZhfjstPyezQsO0R7XKIfsKUoec9+8336q9AHh0u79gep dLPNVe50WSbaXmXU/1WGaerRz6LZ+d3P4mWSLkX8SNJOEy+zZc52Zex+IXUif5uhAMehI90S x8Unel7W2u0/t3v1/t0pSizFGYmGWsxFxYkAR03BfqcCAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch modifies Exynos Power Domain driver initialization implementation in following way: - Added platform driver support and probe function where Exynos PM Domain driver will register itself as MFD PMU client driver. - This driver will now use the PMU base address with certain offset for power domain register address so reg property is not required. This change will avoid unnecessary ioremap of the power register. - PMU base address is directly accessed and syscon interface is not used as PM Domain driver is quite critical and syscon based lock protected register access(regmap) is not used. Cc: Kukjin Kim Reviewed-by: Pankaj Dubey Signed-off-by: Amit Daniel Kachhap --- .../bindings/arm/exynos/power_domain.txt | 8 +-- arch/arm/mach-exynos/pm_domains.c | 59 ++++++++++++++------ 2 files changed, 47 insertions(+), 20 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt index abde1ea..5599017 100644 --- a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt +++ b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt @@ -6,8 +6,8 @@ to gate power to one or more peripherals on the processor. Required Properties: - compatible: should be one of the following. * samsung,exynos4210-pd - for exynos4210 type power domain. -- reg: physical base address of the controller and length of memory mapped - region. +- pd-offset: this gives the offset of PM power domain register from + the PMU base address. - #power-domain-cells: number of cells in power domain specifier; must be 0. @@ -30,13 +30,13 @@ Example: lcd0: power-domain-lcd0 { compatible = "samsung,exynos4210-pd"; - reg = <0x10023C00 0x10>; + pd-offset = <0x3C00>; #power-domain-cells = <0>; }; mfc_pd: power-domain@10044060 { compatible = "samsung,exynos4210-pd"; - reg = <0x10044060 0x20>; + pd-offset = <0x4060>; clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK333>, <&clock CLK_MOUT_USER_ACLK333>; clock-names = "oscclk", "pclk0", "clk0"; diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c index 20f2671..923eb57 100644 --- a/arch/arm/mach-exynos/pm_domains.c +++ b/arch/arm/mach-exynos/pm_domains.c @@ -22,6 +22,7 @@ #include #include #include +#include #define INT_LOCAL_PWR_EN 0x7 #define MAX_CLK_PER_DOMAIN 4 @@ -105,33 +106,41 @@ static int exynos_pd_power_off(struct generic_pm_domain *domain) return exynos_pd_power(domain, false); } -static __init int exynos4_pm_init_power_domain(void) +static int exynos_power_domain_probe(struct platform_device *pdev) { - struct platform_device *pdev; struct device_node *np; + struct pmu_dev_client_data *pdata = NULL; + void __iomem *pmu_base_addr; + unsigned int offset; + + pdata = pdev->dev.platform_data; + if (!pdata) { + dev_err(&pdev->dev, "No platform data passed\n"); + return -EINVAL; + } + + pmu_base_addr = pdata->mem_base_addr; for_each_compatible_node(np, NULL, "samsung,exynos4210-pd") { struct exynos_pm_domain *pd; int on, i; - struct device *dev; - pdev = of_find_device_by_node(np); - dev = &pdev->dev; - - pd = kzalloc(sizeof(*pd), GFP_KERNEL); - if (!pd) { - pr_err("%s: failed to allocate memory for domain\n", - __func__); + pd = devm_kzalloc(&pdev->dev, sizeof(*pd), GFP_KERNEL); + if (!pd) return -ENOMEM; - } pd->pd.name = kstrdup(np->name, GFP_KERNEL); pd->name = pd->pd.name; - pd->base = of_iomap(np, 0); + if (of_property_read_u32(np, "pd-offset", &offset)) { + pr_err("%s: failed to find offset for power domain\n", + __func__); + return -EINVAL; + } + pd->base = pmu_base_addr + offset; pd->pd.power_off = exynos_pd_power_off; pd->pd.power_on = exynos_pd_power_on; - pd->oscclk = clk_get(dev, "oscclk"); + pd->oscclk = of_clk_get_by_name(np, "oscclk"); if (IS_ERR(pd->oscclk)) goto no_clk; @@ -139,11 +148,11 @@ static __init int exynos4_pm_init_power_domain(void) char clk_name[8]; snprintf(clk_name, sizeof(clk_name), "clk%d", i); - pd->clk[i] = clk_get(dev, clk_name); + pd->clk[i] = of_clk_get_by_name(np, clk_name); if (IS_ERR(pd->clk[i])) break; snprintf(clk_name, sizeof(clk_name), "pclk%d", i); - pd->pclk[i] = clk_get(dev, clk_name); + pd->pclk[i] = of_clk_get_by_name(np, clk_name); if (IS_ERR(pd->pclk[i])) { clk_put(pd->clk[i]); pd->clk[i] = ERR_PTR(-EINVAL); @@ -163,4 +172,22 @@ no_clk: return 0; } -arch_initcall(exynos4_pm_init_power_domain); + +static const struct platform_device_id exynos_power_domain_id[] = { + { "exynos-pmu-domain"}, + { }, +}; + +static struct platform_driver exynos_power_domain_driver = { + .driver = { + .name = "exynos-pd", + }, + .probe = exynos_power_domain_probe, + .id_table = exynos_power_domain_id, +}; + +static int __init exynos_power_domain_init(void) +{ + return platform_driver_register(&exynos_power_domain_driver); +} +postcore_initcall(exynos_power_domain_init);