From patchwork Thu Mar 12 12:15:11 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vince Hsu X-Patchwork-Id: 5993611 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id CDDBEBF90F for ; Thu, 12 Mar 2015 12:18:31 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C90FE2039C for ; Thu, 12 Mar 2015 12:18:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B93C020397 for ; Thu, 12 Mar 2015 12:18:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754064AbbCLMQJ (ORCPT ); Thu, 12 Mar 2015 08:16:09 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:16234 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753828AbbCLMQF (ORCPT ); Thu, 12 Mar 2015 08:16:05 -0400 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Thu, 12 Mar 2015 05:16:37 -0700 Received: from hqemhub03.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Thu, 12 Mar 2015 05:14:30 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Thu, 12 Mar 2015 05:14:30 -0700 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQEMHUB03.nvidia.com (172.20.150.15) with Microsoft SMTP Server id 8.3.342.0; Thu, 12 Mar 2015 05:16:04 -0700 Received: from vinceh-linux.nvidia.com (Not Verified[10.19.108.63]) by hqnvemgw01.nvidia.com with MailMarshal (v7,1,2,5326) id ; Thu, 12 Mar 2015 05:16:03 -0700 From: Vince Hsu To: thierry.reding@gmail.com, pdeschrijver@nvidia.com, swarren@wwwdotorg.org, gnurou@gmail.com, jroedel@suse.de, p.zabel@pengutronix.de, mturquette@linaro.org, pgaikwad@nvidia.com, sboyd@codeaurora.org, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux@arm.linux.org.uk, tbergstrom@nvidia.com, airlied@linux.ie, bhelgaas@google.com, tj@kernel.org, arnd@arndb.de, robh@kernel.org, will.deacon@arm.com CC: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, rjw@rjwysocki.net, viresh.kumar@linaro.org, Vince Hsu Subject: [PATCH v2 10/17] ARM: tegra: add PM domain device nodes to Tegra124 DT Date: Thu, 12 Mar 2015 20:15:11 +0800 Message-ID: <1426162518-7405-11-git-send-email-vinceh@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1426162518-7405-1-git-send-email-vinceh@nvidia.com> References: <1426162518-7405-1-git-send-email-vinceh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Also bind the PM domain provider and consumer together. Signed-off-by: Vince Hsu --- arch/arm/boot/dts/tegra124.dtsi | 86 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 85 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 4be06c6ea0c8..0ef15136d829 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -3,6 +3,7 @@ #include #include #include +#include #include #include @@ -39,6 +40,8 @@ 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ + power-domains = <&pmc TEGRA_POWERGATE_PCIE>; + clocks = <&tegra_car TEGRA124_CLK_PCIE>, <&tegra_car TEGRA124_CLK_AFI>, <&tegra_car TEGRA124_CLK_PLL_E>, @@ -98,6 +101,7 @@ compatible = "nvidia,tegra124-dc"; reg = <0x0 0x54200000 0x0 0x00040000>; interrupts = ; + power-domains = <&pmc TEGRA_POWERGATE_DIS>; clocks = <&tegra_car TEGRA124_CLK_DISP1>, <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "dc", "parent"; @@ -113,6 +117,7 @@ compatible = "nvidia,tegra124-dc"; reg = <0x0 0x54240000 0x0 0x00040000>; interrupts = ; + power-domains = <&pmc TEGRA_POWERGATE_DISB>; clocks = <&tegra_car TEGRA124_CLK_DISP2>, <&tegra_car TEGRA124_CLK_PLL_P>; clock-names = "dc", "parent"; @@ -140,6 +145,7 @@ compatible = "nvidia,tegra124-sor"; reg = <0x0 0x54540000 0x0 0x00040000>; interrupts = ; + power-domains = <&pmc TEGRA_POWERGATE_SOR>; clocks = <&tegra_car TEGRA124_CLK_SOR0>, <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, <&tegra_car TEGRA124_CLK_PLL_DP>, @@ -182,6 +188,7 @@ interrupts = , ; interrupt-names = "stall", "nonstall"; + power-domains = <&pmc TEGRA_POWERGATE_3D>; clocks = <&tegra_car TEGRA124_CLK_GPU>, <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; clock-names = "gpu", "pwr"; @@ -542,11 +549,86 @@ clocks = <&tegra_car TEGRA124_CLK_RTC>; }; - pmc@0,7000e400 { + pmc: pmc@0,7000e400 { compatible = "nvidia,tegra124-pmc"; reg = <0x0 0x7000e400 0x0 0x400>; clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; + #power-domain-cells = <1>; + }; + + dcpd: dc-power-domain { + compatible = "nvidia,power-domains"; + name = "dc-power-domain"; + domain = ; + clocks = <&tegra_car TEGRA124_CLK_DISP1>; + resets = <&tegra_car 27>; + nvidia,swgroup = <&mc TEGRA_SWGROUP_DC>; + depend-on = <&sorpd>; + }; + + dcb-power-domain { + compatible = "nvidia,power-domains"; + name = "dcb-power-domain"; + domain = ; + clocks = <&tegra_car TEGRA124_CLK_DISP2>; + resets = <&tegra_car 26>; + nvidia,swgroup = <&mc TEGRA_SWGROUP_DCB>; + depend-on = <&dcpd>; + }; + + pcie-power-domain { + compatible = "nvidia,power-domains"; + name = "pcie-power-domain"; + domain = ; + clocks = <&tegra_car TEGRA124_CLK_PCIE>, + <&tegra_car TEGRA124_CLK_AFI>, + <&tegra_car TEGRA124_CLK_CML0>; + resets = <&tegra_car 70>, + <&tegra_car 72>, + <&tegra_car 74>; + nvidia,swgroup = <&mc TEGRA_SWGROUP_AFI>; + }; + + sorpd: sor-power-domain { + compatible = "nvidia,power-domains"; + name = "sor-power-domain"; + domain = ; + clocks = <&tegra_car TEGRA124_CLK_SOR0>, + <&tegra_car TEGRA124_CLK_DSIA>, + <&tegra_car TEGRA124_CLK_DSIB>, + <&tegra_car TEGRA124_CLK_HDMI>, + <&tegra_car TEGRA124_CLK_MIPI_CAL>, + <&tegra_car TEGRA124_CLK_DPAUX>; + resets = <&tegra_car 182>, + <&tegra_car 48>, + <&tegra_car 82>, + <&tegra_car 51>, + <&tegra_car 56>; + }; + + gpu-power-domain { + compatible = "nvidia,power-domains"; + name = "gpu-power-domain"; + domain = ; + clocks = <&tegra_car TEGRA124_CLK_GPU>, + <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; + resets = <&tegra_car 184>; + external-power-rail; + nvidia,swgroup = <&mc TEGRA_SWGROUP_GPU>; + }; + + sata-power-domain { + compatible = "nvidia,power-domains"; + name = "sata-power-domain"; + domain = ; + clocks = <&tegra_car TEGRA124_CLK_SATA>, + <&tegra_car TEGRA124_CLK_SATA_OOB>, + <&tegra_car TEGRA124_CLK_CML1>; + resets = <&tegra_car 124>, + <&tegra_car 123>, + <&tegra_car 129>; + nvidia,swgroup = <&mc TEGRA_SWGROUP_SATA>; }; fuse@0,7000f800 { @@ -588,6 +670,8 @@ <&tegra_car 129>; reset-names = "sata", "sata-oob", "sata-cold"; + power-domains = <&pmc TEGRA_POWERGATE_SATA>; + phys = <&padctl TEGRA_XUSB_PADCTL_SATA>; phy-names = "sata-phy";