From patchwork Thu Mar 12 12:15:04 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vince Hsu X-Patchwork-Id: 5993721 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 109189F444 for ; Thu, 12 Mar 2015 12:20:29 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 323FF2039D for ; Thu, 12 Mar 2015 12:20:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C03582039C for ; Thu, 12 Mar 2015 12:20:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752813AbbCLMPZ (ORCPT ); Thu, 12 Mar 2015 08:15:25 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:6982 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754173AbbCLMPU (ORCPT ); Thu, 12 Mar 2015 08:15:20 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Thu, 12 Mar 2015 05:16:00 -0700 Received: from hqemhub03.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Thu, 12 Mar 2015 05:13:11 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Thu, 12 Mar 2015 05:13:11 -0700 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQEMHUB03.nvidia.com (172.20.150.15) with Microsoft SMTP Server id 8.3.342.0; Thu, 12 Mar 2015 05:15:19 -0700 Received: from vinceh-linux.nvidia.com (Not Verified[10.19.108.63]) by hqnvemgw01.nvidia.com with MailMarshal (v7,1,2,5326) id ; Thu, 12 Mar 2015 05:15:19 -0700 From: Vince Hsu To: thierry.reding@gmail.com, pdeschrijver@nvidia.com, swarren@wwwdotorg.org, gnurou@gmail.com, jroedel@suse.de, p.zabel@pengutronix.de, mturquette@linaro.org, pgaikwad@nvidia.com, sboyd@codeaurora.org, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux@arm.linux.org.uk, tbergstrom@nvidia.com, airlied@linux.ie, bhelgaas@google.com, tj@kernel.org, arnd@arndb.de, robh@kernel.org, will.deacon@arm.com CC: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, rjw@rjwysocki.net, viresh.kumar@linaro.org, Vince Hsu Subject: [PATCH v2 03/17] memory: tegra: add flush operation for Tegra30 memory clients Date: Thu, 12 Mar 2015 20:15:04 +0800 Message-ID: <1426162518-7405-4-git-send-email-vinceh@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1426162518-7405-1-git-send-email-vinceh@nvidia.com> References: <1426162518-7405-1-git-send-email-vinceh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the hot reset register table and flush related callback functions for Tegra30. Signed-off-by: Vince Hsu --- drivers/memory/tegra/tegra30.c | 78 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/drivers/memory/tegra/tegra30.c b/drivers/memory/tegra/tegra30.c index 3ed4bf409a72..71ed7ee0aace 100644 --- a/drivers/memory/tegra/tegra30.c +++ b/drivers/memory/tegra/tegra30.c @@ -6,6 +6,8 @@ * published by the Free Software Foundation. */ +#include +#include #include #include @@ -936,6 +938,79 @@ static const struct tegra_smmu_swgroup tegra30_swgroups[] = { { .swgroup = TEGRA_SWGROUP_ISP, .reg = 0x258 }, }; +static struct tegra_mc_hotreset tegra30_mc_hotreset[] = { + {TEGRA_SWGROUP_AFI, 0x200, 0x204, 0}, + {TEGRA_SWGROUP_AVPC, 0x200, 0x204, 1}, + {TEGRA_SWGROUP_DC, 0x200, 0x204, 2}, + {TEGRA_SWGROUP_DCB, 0x200, 0x204, 3}, + {TEGRA_SWGROUP_EPP, 0x200, 0x204, 4}, + {TEGRA_SWGROUP_G2, 0x200, 0x204, 5}, + {TEGRA_SWGROUP_HC, 0x200, 0x204, 6}, + {TEGRA_SWGROUP_HDA, 0x200, 0x204, 7}, + {TEGRA_SWGROUP_ISP, 0x200, 0x204, 8}, + {TEGRA_SWGROUP_MPCORE, 0x200, 0x204, 9}, + {TEGRA_SWGROUP_MPCORELP, 0x200, 0x204, 10}, + {TEGRA_SWGROUP_MPE, 0x200, 0x204, 11}, + {TEGRA_SWGROUP_NV, 0x200, 0x204, 12}, + {TEGRA_SWGROUP_NV2, 0x200, 0x204, 13}, + {TEGRA_SWGROUP_PPCS, 0x200, 0x204, 14}, + {TEGRA_SWGROUP_VDE, 0x200, 0x204, 16}, + {TEGRA_SWGROUP_VI, 0x200, 0x204, 17}, +}; + +static int tegra30_mc_flush(struct tegra_mc *mc, + const struct tegra_mc_hotreset *hotreset) +{ + u32 val; + + if (!mc || !hotreset) + return -EINVAL; + + mutex_lock(&mc->lock); + + val = mc_readl(mc, hotreset->ctrl); + val |= BIT(hotreset->bit); + mc_writel(mc, val, hotreset->ctrl); + mc_readl(mc, hotreset->ctrl); + + mutex_unlock(&mc->lock); + + /* poll till the flush is done */ + do { + udelay(10); + val = mc_readl(mc, hotreset->status); + } while (!(val & BIT(hotreset->bit))); + + dev_dbg(mc->dev, "%s bit %d\n", __func__, hotreset->bit); + return 0; +} + +static int tegra30_mc_flush_done(struct tegra_mc *mc, + const struct tegra_mc_hotreset *hotreset) +{ + u32 val; + + if (!mc || !hotreset) + return -EINVAL; + + mutex_lock(&mc->lock); + + val = mc_readl(mc, hotreset->ctrl); + val &= ~BIT(hotreset->bit); + mc_writel(mc, val, hotreset->ctrl); + mc_readl(mc, hotreset->ctrl); + + mutex_unlock(&mc->lock); + + dev_dbg(mc->dev, "%s bit %d\n", __func__, hotreset->bit); + return 0; +} + +static const struct tegra_mc_ops tegra30_mc_ops = { + .flush = tegra30_mc_flush, + .flush_done = tegra30_mc_flush_done, +}; + static void tegra30_flush_dcache(struct page *page, unsigned long offset, size_t size) { @@ -967,4 +1042,7 @@ const struct tegra_mc_soc tegra30_mc_soc = { .num_address_bits = 32, .atom_size = 16, .smmu = &tegra30_smmu_soc, + .hotresets = tegra30_mc_hotreset, + .num_hotresets = ARRAY_SIZE(tegra30_mc_hotreset), + .ops = &tegra30_mc_ops, };