From patchwork Tue Apr 21 13:17:56 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartlomiej Zolnierkiewicz X-Patchwork-Id: 6248711 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id C4156BF4A6 for ; Tue, 21 Apr 2015 13:20:36 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D7A38202EC for ; Tue, 21 Apr 2015 13:20:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D8C6B20295 for ; Tue, 21 Apr 2015 13:20:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755560AbbDUNUI (ORCPT ); Tue, 21 Apr 2015 09:20:08 -0400 Received: from mailout4.samsung.com ([203.254.224.34]:54151 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752667AbbDUNUF (ORCPT ); Tue, 21 Apr 2015 09:20:05 -0400 Received: from epcpsbgm1.samsung.com (epcpsbgm1 [203.254.230.26]) by mailout4.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NN500LWJROPRL00@mailout4.samsung.com>; Tue, 21 Apr 2015 22:19:37 +0900 (KST) X-AuditID: cbfee61a-f79516d000006302-8d-55364e69d3ca Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id A5.1B.25346.96E46355; Tue, 21 Apr 2015 22:19:37 +0900 (KST) Received: from amdc1032.digital.local ([106.116.147.136]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NN500HX0RM5PL00@mmp2.samsung.com>; Tue, 21 Apr 2015 22:19:37 +0900 (KST) From: Bartlomiej Zolnierkiewicz To: Thomas Abraham , Sylwester Nawrocki , Mike Turquette , Kukjin Kim , Kukjin Kim , Viresh Kumar Cc: Tomasz Figa , Lukasz Majewski , Heiko Stuebner , Chanwoo Choi , Kevin Hilman , Javier Martinez Canillas , linux-samsung-soc@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, b.zolnierkie@samsung.com Subject: [PATCH 6/8] clk: samsung: exynos5800: fix cpu clock configuration data Date: Tue, 21 Apr 2015 15:17:56 +0200 Message-id: <1429622278-12216-7-git-send-email-b.zolnierkie@samsung.com> X-Mailer: git-send-email 1.7.9.5 In-reply-to: <1429622278-12216-1-git-send-email-b.zolnierkie@samsung.com> References: <1429622278-12216-1-git-send-email-b.zolnierkie@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrELMWRmVeSWpSXmKPExsVy+t9jQd1MP7NQgw+TlC02zljPanH9y3NW i/+PXrNaHP1dYNG74CqbRf/j18wWXw+vYLR483Azo8Wmx9dYLS7vmsNm8bn3CKPFjPP7mCye TrjIZnH4TTurRccyRotVu/4wWmz86uEg6PH3+XUWj52z7rJ7bFrVyeZx59oeNo/NS+o9+ras YvTYfm0es8fnTXIBHFFcNimpOZllqUX6dglcGR/3rGUrWC5RcfX9OeYGxrkiXYycHBICJhK7 W1ayQthiEhfurWfrYuTiEBKYzihxYX4DM4Tzm1Fiz4HHzCBVbAJWEhPbVzGCJEQEPjBKvH73 DayFWWA+s8SEp6dYQKqEBfwl7r94BjaXRUBVonfaXzCbV8BDonfDAiCbA2ifgsScSTYgYU4B T4nzl1+ClQgBlUyctZ9xAiPvAkaGVYyiqQXJBcVJ6bmGesWJucWleel6yfm5mxjBIf1Magfj ygaLQ4wCHIxKPLwrJpiGCrEmlhVX5h5ilOBgVhLhFRQyCxXiTUmsrEotyo8vKs1JLT7EKM3B oiTOO0dXLlRIID2xJDU7NbUgtQgmy8TBKdXAOFni32mXe638STYR728F30i7MjWdMVYkPXfP iqeHTU0+sWxp15Q1T8rhqjP8cX+nskNMYdDV5Onrw+sV3jjP/WIZ9SnwYadme7LtJ++qjXpu xQWl3xoOnHLX431lm8byp6DFXdnqufK7vBOc5su6Dh/jz1UR2ND5e+MGvj+GtZG6vpsKjzUp sRRnJBpqMRcVJwIALMC3ZGUCAAA= Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Fix cpu clock configuration data for Exynos5800 (it uses higher PCLK_DBG divider values than Exynos5420 and supports additional frequencies). Based on Hardkernel's kernel for ODROID-XU3 board. Cc: Tomasz Figa Cc: Mike Turquette Cc: Javier Martinez Canillas Cc: Thomas Abraham Signed-off-by: Bartlomiej Zolnierkiewicz Reviewed-by: Lukasz Majewski --- drivers/clk/samsung/clk-exynos5420.c | 36 +++++++++++++++++++++++++++++++--- 1 file changed, 33 insertions(+), 3 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 9398a2d..462aaee 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -1274,10 +1274,34 @@ static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = { { 0 }, }; +static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst = { + { 2000000, E5420_EGL_DIV0(3, 7, 7, 4), }, + { 1900000, E5420_EGL_DIV0(3, 7, 7, 4), }, + { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), }, + { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), }, + { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), }, + { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), }, + { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), }, + { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), }, + { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), }, + { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), }, + { 1000000, E5420_EGL_DIV0(3, 7, 6, 2), }, + { 900000, E5420_EGL_DIV0(3, 7, 6, 2), }, + { 800000, E5420_EGL_DIV0(3, 7, 5, 2), }, + { 700000, E5420_EGL_DIV0(3, 7, 5, 2), }, + { 600000, E5420_EGL_DIV0(3, 7, 4, 2), }, + { 500000, E5420_EGL_DIV0(3, 7, 3, 2), }, + { 400000, E5420_EGL_DIV0(3, 7, 3, 2), }, + { 300000, E5420_EGL_DIV0(3, 7, 3, 2), }, + { 200000, E5420_EGL_DIV0(3, 7, 3, 2), }, + { 0 }, +}; + #define E5420_KFC_DIV(kpll, pclk, aclk) \ ((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4))) static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = { + { 1400000, E5420_KFC_DIV(3, 5, 3), }, /* for Exynos5800 */ { 1300000, E5420_KFC_DIV(3, 5, 2), }, { 1200000, E5420_KFC_DIV(3, 5, 2), }, { 1100000, E5420_KFC_DIV(3, 5, 2), }, @@ -1357,9 +1381,15 @@ static void __init exynos5x_clk_init(struct device_node *np, ARRAY_SIZE(exynos5800_gate_clks)); } - exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", - mout_cpu_p[0], mout_cpu_p[1], 0x200, - exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0); + if (soc == EXYNOS5420) { + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", + mout_cpu_p[0], mout_cpu_p[1], 0x200, + exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0); + } else { + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", + mout_cpu_p[0], mout_cpu_p[1], 0x200, + exynos5800_eglclk_d, ARRAY_SIZE(exynos5800_eglclk_d), 0); + } exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk", mout_kfc_p[0], mout_kfc_p[1], 0x28200, exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0);