From patchwork Fri Jul 3 06:11:55 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 6712931 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id BF7DCC05AC for ; Fri, 3 Jul 2015 06:13:24 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D60E3204FB for ; Fri, 3 Jul 2015 06:13:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C3D58201CD for ; Fri, 3 Jul 2015 06:13:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754617AbbGCGNV (ORCPT ); Fri, 3 Jul 2015 02:13:21 -0400 Received: from down.free-electrons.com ([37.187.137.238]:55198 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752981AbbGCGMO (ORCPT ); Fri, 3 Jul 2015 02:12:14 -0400 Received: by mail.free-electrons.com (Postfix, from userid 106) id 32B811F4E; Fri, 3 Jul 2015 08:12:13 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from localhost (von69-1-88-162-9-206.fbx.proxad.net [88.162.9.206]) by mail.free-electrons.com (Postfix) with ESMTPSA id AA62A66B; Fri, 3 Jul 2015 08:12:12 +0200 (CEST) From: Gregory CLEMENT To: Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Gregory CLEMENT Cc: Thomas Petazzoni , Ezequiel Garcia , linux-arm-kernel@lists.infradead.org, Mike Turquette , Stephen Boyd , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Daniel Lezcano , "Rafael J. Wysocki" , linux-pm@vger.kernel.org, Maxime Ripard , Boris BREZILLON , Lior Amsalem , Tawfik Bayouk , Nadav Haklai Subject: [PATCH RFC 3/5] ARM: mvebu: Made the dynamic frequency scaling support more generic Date: Fri, 3 Jul 2015 08:11:55 +0200 Message-Id: <1435903917-20486-4-git-send-email-gregory.clement@free-electrons.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1435903917-20486-1-git-send-email-gregory.clement@free-electrons.com> References: <1435903917-20486-1-git-send-email-gregory.clement@free-electrons.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In preparation to support cpufreq for Armada 38x: - rename the function to be more generic. - move masking interrupt to the _dfs_request_local function in order to be use by both SoCs. - add stubs allowing registering the support for a new SoC Signed-off-by: Gregory CLEMENT --- arch/arm/mach-mvebu/pmsu.c | 48 +++++++++++++++++++++++++--------------------- 1 file changed, 26 insertions(+), 22 deletions(-) diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c index d207f5fc13a6..f19be0ac0068 100644 --- a/arch/arm/mach-mvebu/pmsu.c +++ b/arch/arm/mach-mvebu/pmsu.c @@ -105,6 +105,7 @@ static phys_addr_t pmsu_mp_phys_base; static void __iomem *pmsu_mp_base; static void *mvebu_cpu_resume; +static int (*mvebu_pmsu_dfs_request_ptr)(int cpu); static const struct of_device_id of_pmsu_table[] = { { .compatible = "marvell,armada-370-pmsu", }, @@ -522,6 +523,14 @@ static void mvebu_pmsu_dfs_request_local(void *data) local_irq_save(flags); + /* Clear any previous DFS DONE event */ + reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_MSK(cpu)); + reg &= ~PMSU_EVENT_STATUS_MSK_DFS_DONE; + + /* Mask the DFS done interrupt, since we are going to poll */ + reg |= PMSU_EVENT_STATUS_MSK_DFS_DONE_MASK; + writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_MSK(cpu)); + /* Prepare to enter idle */ reg = readl(pmsu_mp_base + PMSU_STATUS_MSK(cpu)); reg |= PMSU_STATUS_MSK_CPU_IDLE_WAIT | @@ -545,25 +554,20 @@ static void mvebu_pmsu_dfs_request_local(void *data) reg &= ~PMSU_STATUS_MSK_CPU_IDLE_WAIT; writel(reg, pmsu_mp_base + PMSU_STATUS_MSK(cpu)); + /* Restore the DFS mask to its original state */ + reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_MSK(cpu)); + reg &= ~PMSU_EVENT_STATUS_MSK_DFS_DONE_MASK; + writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_MSK(cpu)); + local_irq_restore(flags); } -int mvebu_pmsu_dfs_request(int cpu) +int armada_xp_pmsu_dfs_request(int cpu) { unsigned long timeout; int hwcpu = cpu_logical_map(cpu); u32 reg; - /* Clear any previous DFS DONE event */ - reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu)); - reg &= ~PMSU_EVENT_STATUS_AND_MASK_DFS_DONE; - writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu)); - - /* Mask the DFS done interrupt, since we are going to poll */ - reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu)); - reg |= PMSU_EVENT_STATUS_AND_MASK_DFS_DONE_MASK; - writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu)); - /* Trigger the DFS on the appropriate CPU */ smp_call_function_single(cpu, mvebu_pmsu_dfs_request_local, NULL, false); @@ -579,20 +583,19 @@ int mvebu_pmsu_dfs_request(int cpu) if (time_after(jiffies, timeout)) return -ETIME; - - /* Restore the DFS mask to its original state */ - reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu)); - reg &= ~PMSU_EVENT_STATUS_AND_MASK_DFS_DONE_MASK; - writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu)); - return 0; } -struct cpufreq_dt_platform_data cpufreq_dt_pd = { +int mvebu_pmsu_dfs_request(int cpu) +{ + return mvebu_pmsu_dfs_request_ptr(cpu); +} + +struct cpufreq_dt_platform_data armada_xp_cpufreq_dt_pd = { .independent_clocks = true, }; -static int __init armada_xp_pmsu_cpufreq_init(void) +static int __init mvebu_pmsu_cpufreq_init(void) { struct device_node *np; struct resource res; @@ -663,10 +666,11 @@ static int __init armada_xp_pmsu_cpufreq_init(void) return ret; } } - + mvebu_pmsu_dfs_request_ptr = armada_xp_pmsu_dfs_request; platform_device_register_data(NULL, "cpufreq-dt", -1, - &cpufreq_dt_pd, sizeof(cpufreq_dt_pd)); + &armada_xp_cpufreq_dt_pd, + sizeof(armada_xp_cpufreq_dt_pd)); return 0; } -device_initcall(armada_xp_pmsu_cpufreq_init); +device_initcall(mvebu_pmsu_cpufreq_init);