From patchwork Mon Aug 3 15:22:53 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Punit Agrawal X-Patchwork-Id: 6930511 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 10D6EC05AC for ; Mon, 3 Aug 2015 15:26:29 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3C95420626 for ; Mon, 3 Aug 2015 15:26:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A4030205E1 for ; Mon, 3 Aug 2015 15:26:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753971AbbHCPYN (ORCPT ); Mon, 3 Aug 2015 11:24:13 -0400 Received: from fw-tnat.cambridge.arm.com ([217.140.96.140]:28765 "EHLO cam-smtp0.cambridge.arm.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752203AbbHCPYM (ORCPT ); Mon, 3 Aug 2015 11:24:12 -0400 Received: from e105922-lin.cambridge.arm.com (e105922-lin.cambridge.arm.com [10.2.135.144]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with SMTP id t73FMjSx017929; Mon, 3 Aug 2015 16:22:45 +0100 Received: by e105922-lin.cambridge.arm.com (sSMTP sendmail emulation); Mon, 03 Aug 2015 16:24:04 +0100 From: Punit Agrawal To: linux-pm@vger.kernel.org Cc: Punit Agrawal , lm-sensors@lm-sensors.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, liviu.dudau@arm.com, Rob Herring , Mark Rutland , Sudeep Holla Subject: [PATCH v2 05/10] Documentation: add DT bindings for ARM SCPI sensors Date: Mon, 3 Aug 2015 16:22:53 +0100 Message-Id: <1438615378-14241-6-git-send-email-punit.agrawal@arm.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1438615378-14241-1-git-send-email-punit.agrawal@arm.com> References: <1438615378-14241-1-git-send-email-punit.agrawal@arm.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The System Control Processor (SCP) provides access to SoC sensors via the System Control and Power Interface (SCPI) Message Protocol. Add bindings to allow probing of these sensors. Also support referencing of the sensors for setting up thermal zones via the thermal DT bindings. Signed-off-by: Punit Agrawal Cc: Rob Herring Cc: Mark Rutland Cc: Sudeep Holla --- Documentation/devicetree/bindings/arm/arm,scpi.txt | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/arm,scpi.txt b/Documentation/devicetree/bindings/arm/arm,scpi.txt index e309249..8ead68a 100644 --- a/Documentation/devicetree/bindings/arm/arm,scpi.txt +++ b/Documentation/devicetree/bindings/arm/arm,scpi.txt @@ -72,8 +72,18 @@ Required sub-node properties: - compatible : should be "arm,juno-scp-shmem" for Non-secure SRAM based shared memory on Juno platforms +Sensor bindings for the sensors based on SCPI Message Protocol +-------------------------------------------------------------- +SCPI provides an API to access the various sensors on the SoC. + +Required properties: +- compatible : should be "arm,scpi-sensors". +- #thermal-sensor-cells: should be set to 1. This property follows the + thermal device tree bindings[2]. + [0] http://community.arm.com/servlet/JiveServlet/download/8401-45-18326/DUI0922B_scp_message_interface.pdf [1] Documentation/devicetree/bindings/clock/clock-bindings.txt +[2] Documentation/devicetree/bindings/thermal/thermal.txt Example: @@ -122,6 +132,11 @@ scpi_protocol: scpi@2e000000 { clock-output-names = "pxlclk0", "pxlclk1"; }; }; + + scpi_sensors0: sensors { + compatible = "arm,scpi-sensors"; + #thermal-sensor-cells = <1>; + }; }; cpu@0 {