From patchwork Thu Aug 6 10:37:45 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajendra Nayak X-Patchwork-Id: 6957781 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 10976C05AC for ; Thu, 6 Aug 2015 10:39:45 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 0FB6B20675 for ; Thu, 6 Aug 2015 10:39:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 093B92068A for ; Thu, 6 Aug 2015 10:39:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755409AbbHFKji (ORCPT ); Thu, 6 Aug 2015 06:39:38 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:38650 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755383AbbHFKj2 (ORCPT ); Thu, 6 Aug 2015 06:39:28 -0400 Received: from smtp.codeaurora.org (localhost [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id 0559F141551; Thu, 6 Aug 2015 10:39:28 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 486) id E5536141552; Thu, 6 Aug 2015 10:39:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from blr-ubuntu-34.ap.qualcomm.com (unknown [202.46.23.61]) (using TLSv1.1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: rnayak@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 38B56141540; Thu, 6 Aug 2015 10:39:18 +0000 (UTC) From: Rajendra Nayak To: sboyd@codeaurora.org, mturquette@baylibre.com Cc: linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, georgi.djakov@linaro.org, svarbanov@mm-sol.com, srinivas.kandagatla@linaro.org, sviau@codeaurora.org, Rajendra Nayak Subject: [PATCH v8 04/13] clk: qcom: gdsc: Add support for ON only state Date: Thu, 6 Aug 2015 16:07:45 +0530 Message-Id: <1438857474-20262-5-git-send-email-rnayak@codeaurora.org> X-Mailer: git-send-email 1.8.2.1 In-Reply-To: <1438857474-20262-1-git-send-email-rnayak@codeaurora.org> References: <1438857474-20262-1-git-send-email-rnayak@codeaurora.org> X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Certain devices can have GDSCs' which support ON as the only state. They can't be power collapsed to either hit RET or OFF. The clients drivers for these GDSCs' however would expect the state of the core to be reset following a GDSC disable and re-enable. To do this assert/deassert reset lines every time the client driver would request the GDSC to be powered on/off instead. Signed-off-by: Rajendra Nayak --- drivers/clk/qcom/common.c | 3 ++- drivers/clk/qcom/gdsc.c | 35 ++++++++++++++++++++++++++++++++++- drivers/clk/qcom/gdsc.h | 11 ++++++++++- 3 files changed, 46 insertions(+), 3 deletions(-) diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c index a319aa8..4bc87e1 100644 --- a/drivers/clk/qcom/common.c +++ b/drivers/clk/qcom/common.c @@ -124,7 +124,8 @@ int qcom_cc_really_probe(struct platform_device *pdev, goto err_reset; if (desc->gdscs && desc->num_gdscs) { - ret = gdsc_register(dev, desc->gdscs, desc->num_gdscs, regmap); + ret = gdsc_register(dev, desc->gdscs, desc->num_gdscs, + &reset->rcdev, regmap); if (ret) goto err_pd; } diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c index e6bbb76..da9fad8 100644 --- a/drivers/clk/qcom/gdsc.c +++ b/drivers/clk/qcom/gdsc.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include "gdsc.h" @@ -84,6 +85,24 @@ static int gdsc_toggle_logic(struct gdsc *sc, bool en) return -ETIMEDOUT; } +static inline int gdsc_deassert_reset(struct gdsc *sc) +{ + int i; + + for (i = 0; i < sc->reset_count; i++) + sc->rcdev->ops->deassert(sc->rcdev, sc->resets[i]); + return 0; +} + +static inline int gdsc_assert_reset(struct gdsc *sc) +{ + int i; + + for (i = 0; i < sc->reset_count; i++) + sc->rcdev->ops->assert(sc->rcdev, sc->resets[i]); + return 0; +} + static inline void gdsc_force_mem_on(struct gdsc *sc) { int i; @@ -107,6 +126,9 @@ static int gdsc_enable(struct generic_pm_domain *domain) struct gdsc *sc = domain_to_gdsc(domain); int ret; + if (sc->pwrsts == PWRSTS_ON) + return gdsc_deassert_reset(sc); + ret = gdsc_toggle_logic(sc, true); if (ret) return ret; @@ -130,6 +152,9 @@ static int gdsc_disable(struct generic_pm_domain *domain) { struct gdsc *sc = domain_to_gdsc(domain); + if (sc->pwrsts == PWRSTS_ON) + return gdsc_assert_reset(sc); + if (sc->pwrsts & PWRSTS_OFF) gdsc_clear_mem_on(sc); @@ -153,6 +178,13 @@ static int gdsc_init(struct gdsc *sc) if (ret) return ret; + /* Force gdsc ON if only ON state is supported */ + if (sc->pwrsts == PWRSTS_ON) { + ret = gdsc_toggle_logic(sc, true); + if (ret) + return ret; + } + on = gdsc_is_enabled(sc); if (on < 0) return on; @@ -170,7 +202,7 @@ static int gdsc_init(struct gdsc *sc) } int gdsc_register(struct device *dev, struct gdsc **scs, size_t num, - struct regmap *regmap) + struct reset_controller_dev *rcdev, struct regmap *regmap) { int i, ret; struct genpd_onecell_data *data; @@ -189,6 +221,7 @@ int gdsc_register(struct device *dev, struct gdsc **scs, size_t num, if (!scs[i]) continue; scs[i]->regmap = regmap; + scs[i]->rcdev = rcdev; ret = gdsc_init(scs[i]); if (ret) return ret; diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h index 0ff251a..5ded268 100644 --- a/drivers/clk/qcom/gdsc.h +++ b/drivers/clk/qcom/gdsc.h @@ -18,6 +18,7 @@ #include struct regmap; +struct reset_controller_dev; /* Powerdomain allowable state bitfields */ #define PWRSTS_OFF BIT(0) @@ -34,6 +35,9 @@ struct regmap; * @cxcs: offsets of branch registers to toggle mem/periph bits in * @cxc_count: number of @cxcs * @pwrsts: Possible powerdomain power states + * @resets: ids of resets associated with this gdsc + * @reset_count: number of @resets + * @rcdev: reset controller */ struct gdsc { struct generic_pm_domain pd; @@ -42,13 +46,18 @@ struct gdsc { unsigned int *cxcs; unsigned int cxc_count; const u8 pwrsts; + struct reset_controller_dev *rcdev; + unsigned int *resets; + unsigned int reset_count; }; #ifdef CONFIG_QCOM_GDSC -int gdsc_register(struct device *, struct gdsc **, size_t n, struct regmap *); +int gdsc_register(struct device *, struct gdsc **, size_t n, + struct reset_controller_dev *, struct regmap *); void gdsc_unregister(struct device *); #else static inline int gdsc_register(struct device *d, struct gdsc **g, size_t n, + struct reset_controller_dev *rcdev, struct regmap *r) { return -ENOSYS;