From patchwork Fri Aug 28 11:49:35 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartlomiej Zolnierkiewicz X-Patchwork-Id: 7091311 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 1D5E99F1C2 for ; Fri, 28 Aug 2015 11:50:45 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2FDCE20880 for ; Fri, 28 Aug 2015 11:50:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 62ED620873 for ; Fri, 28 Aug 2015 11:50:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751821AbbH1LuU (ORCPT ); Fri, 28 Aug 2015 07:50:20 -0400 Received: from mailout4.samsung.com ([203.254.224.34]:39178 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751833AbbH1LuK (ORCPT ); Fri, 28 Aug 2015 07:50:10 -0400 Received: from epcpsbgm1new.samsung.com (epcpsbgm1 [203.254.230.26]) by mailout4.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NTS02NPZJJ6KPA0@mailout4.samsung.com>; Fri, 28 Aug 2015 20:50:08 +0900 (KST) X-AuditID: cbfee61a-f79a06d000005c6f-13-55e04af09c1d Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1new.samsung.com (EPCPMTA) with SMTP id 24.9A.23663.0FA40E55; Fri, 28 Aug 2015 20:50:08 +0900 (KST) Received: from AMDC1976.DIGITAL.local ([106.120.53.102]) by mmp1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NTS00K4GJJ7DF40@mmp1.samsung.com>; Fri, 28 Aug 2015 20:50:08 +0900 (KST) From: Bartlomiej Zolnierkiewicz To: Michael Turquette Cc: Thomas Abraham , Sylwester Nawrocki , Kukjin Kim , Kukjin Kim , Viresh Kumar , Krzysztof Kozlowski , Dan Carpenter , Tomasz Figa , Lukasz Majewski , Heiko Stuebner , Chanwoo Choi , Kevin Hilman , Javier Martinez Canillas , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, b.zolnierkie@samsung.com Subject: [PATCH v2] clk: samsung: fix cpu clock's flags checking Date: Fri, 28 Aug 2015 13:49:35 +0200 Message-id: <1440762575-21520-1-git-send-email-b.zolnierkie@samsung.com> X-Mailer: git-send-email 1.9.1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrILMWRmVeSWpSXmKPExsVy+t9jAd0PXg9CDZ5OELTYOGM9q8X1L89Z LV7/m85i8f/Ra1aLa79nsFm8fmFo0bvgKptF/+PXzBZfD69gtHjzcDOjxabH11gtPvbcY7W4 vGsOm8Xn3iOMFjPO72OyuHjK1eLwm3ZWi45ljBardv1htNj41cNBxOP9jVZ2j7+zW5k9ds66 y+6xaVUnm8eda3vYPDYvqff4+PQWi0ffllWMHtuvzWP2+LxJLoArissmJTUnsyy1SN8ugSvj 1nSNglmSFR/7WBsYp4t2MXJySAiYSCybcpQVwhaTuHBvPRuILSSwlFHi3lyrLkYuIPsXo8Sh 9nWMIAk2ASuJie2rwGwRAX2Jpgf/2ECKmAUuskr0NTewgCSEBRwktnw9CzSVg4NFQFVi7d8S kDCvgIfEpHdNLBDL5CROHpvMOoGRewEjwypGidSC5ILipPRcw7zUcr3ixNzi0rx0veT83E2M 4IB+JrWD8eAu90OMAhyMSjy8FhvuhwqxJpYVV+YeYpTgYFYS4Q0RehAqxJuSWFmVWpQfX1Sa k1p8iFGag0VJnFd2w+ZQIYH0xJLU7NTUgtQimCwTB6dUA6OU316H3bHfIo+d0zI4/GdxSdPv oD9fOpdsqWPwbA1M2cj393yaTO11v8DdV+K6lr/kS9xd5ZO/qLK3YY91UbrXqkn3q6dNiVTd v+D/xFkeDwpVd96O/5MX9uZO1dz288o+cpuTGpb2d/XLxXdFN2p4MywWWbYptdrHa2fBnQtN u+8dOzTliYkSS3FGoqEWc1FxIgDoh/hRZAIAAA== Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-8.3 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP CLK_CPU_HAS_DIV1 and CLK_CPU_NEEDS_DEBUG_ALT_DIV masks were incorrectly used as a bit numbers. Fix it. Tested on Exynos4210 based Origen board and on Exynos5250 based Arndale board. Cc: Tomasz Figa Cc: Michael Turquette Cc: Thomas Abraham Fixes: ddeac8d96 ("clk: samsung: add infrastructure to register cpu clocks") Reported-by: Dan Carpenter Reviewed-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Acked-by: Sylwester Nawrocki Signed-off-by: Bartlomiej Zolnierkiewicz --- v2: - added Reviewed-by, Acked-by and Fixes tags (no code changes) Michael, please apply. Thank you. drivers/clk/samsung/clk-cpu.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c index 7c1e1f5..2fe37f7 100644 --- a/drivers/clk/samsung/clk-cpu.c +++ b/drivers/clk/samsung/clk-cpu.c @@ -164,7 +164,7 @@ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata, * the values for DIV_COPY and DIV_HPM dividers need not be set. */ div0 = cfg_data->div0; - if (test_bit(CLK_CPU_HAS_DIV1, &cpuclk->flags)) { + if (cpuclk->flags & CLK_CPU_HAS_DIV1) { div1 = cfg_data->div1; if (readl(base + E4210_SRC_CPU) & E4210_MUX_HPM_MASK) div1 = readl(base + E4210_DIV_CPU1) & @@ -185,7 +185,7 @@ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata, alt_div = DIV_ROUND_UP(alt_prate, tmp_rate) - 1; WARN_ON(alt_div >= MAX_DIV); - if (test_bit(CLK_CPU_NEEDS_DEBUG_ALT_DIV, &cpuclk->flags)) { + if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) { /* * In Exynos4210, ATB clock parent is also mout_core. So * ATB clock also needs to be mantained at safe speed. @@ -206,7 +206,7 @@ static int exynos_cpuclk_pre_rate_change(struct clk_notifier_data *ndata, writel(div0, base + E4210_DIV_CPU0); wait_until_divider_stable(base + E4210_DIV_STAT_CPU0, DIV_MASK_ALL); - if (test_bit(CLK_CPU_HAS_DIV1, &cpuclk->flags)) { + if (cpuclk->flags & CLK_CPU_HAS_DIV1) { writel(div1, base + E4210_DIV_CPU1); wait_until_divider_stable(base + E4210_DIV_STAT_CPU1, DIV_MASK_ALL); @@ -225,7 +225,7 @@ static int exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata, unsigned long mux_reg; /* find out the divider values to use for clock data */ - if (test_bit(CLK_CPU_NEEDS_DEBUG_ALT_DIV, &cpuclk->flags)) { + if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) { while ((cfg_data->prate * 1000) != ndata->new_rate) { if (cfg_data->prate == 0) return -EINVAL; @@ -240,7 +240,7 @@ static int exynos_cpuclk_post_rate_change(struct clk_notifier_data *ndata, writel(mux_reg & ~(1 << 16), base + E4210_SRC_CPU); wait_until_mux_stable(base + E4210_STAT_CPU, 16, 1); - if (test_bit(CLK_CPU_NEEDS_DEBUG_ALT_DIV, &cpuclk->flags)) { + if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) { div |= (cfg_data->div0 & E4210_DIV0_ATB_MASK); div_mask |= E4210_DIV0_ATB_MASK; }