From patchwork Tue Nov 17 06:05:47 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pankaj Dubey X-Patchwork-Id: 7633211 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 82C699F1C2 for ; Tue, 17 Nov 2015 06:12:31 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id ADF5620531 for ; Tue, 17 Nov 2015 06:12:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 78DAE2052F for ; Tue, 17 Nov 2015 06:12:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752028AbbKQGMY (ORCPT ); Tue, 17 Nov 2015 01:12:24 -0500 Received: from mailout3.samsung.com ([203.254.224.33]:53972 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752013AbbKQGMW (ORCPT ); Tue, 17 Nov 2015 01:12:22 -0500 Received: from epcpsbgr5.samsung.com (u145.gpu120.samsung.co.kr [203.254.230.145]) by mailout3.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NXY034MM3VWYK80@mailout3.samsung.com>; Tue, 17 Nov 2015 15:11:56 +0900 (KST) Received: from epcpsbgm1new.samsung.com ( [172.20.52.123]) by epcpsbgr5.samsung.com (EPCPMTA) with SMTP id E0.9A.05385.C25CA465; Tue, 17 Nov 2015 15:11:56 +0900 (KST) X-AuditID: cbfee691-f79d66d000001509-86-564ac52c4fa9 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1new.samsung.com (EPCPMTA) with SMTP id E6.C1.23663.C25CA465; Tue, 17 Nov 2015 15:11:56 +0900 (KST) Received: from chromebld-server.sisodomain.com ([107.108.73.106]) by mmp2.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NXY00GBB3PUDS00@mmp2.samsung.com>; Tue, 17 Nov 2015 15:11:55 +0900 (KST) From: Pankaj Dubey To: linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org Cc: kgene.kim@samsung.com, k.kozlowski@samsung.com, thomas.ab@samsung.com, amitdanielk@gmail.com, olof@lixom.net, khilman@linaro.org, arnd@arndb.de, Pankaj Dubey Subject: [PATCH v6 5/9] ARM: EXYNOS: split up exynos4 SoC specific PMU data Date: Tue, 17 Nov 2015 11:35:47 +0530 Message-id: <1447740351-14246-6-git-send-email-pankaj.dubey@samsung.com> X-Mailer: git-send-email 2.4.5 In-reply-to: <1447740351-14246-1-git-send-email-pankaj.dubey@samsung.com> References: <1447740351-14246-1-git-send-email-pankaj.dubey@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrLLMWRmVeSWpSXmKPExsWyRsSkWlfnqFeYwe854hYfV79ks/g76Ri7 xesXhha9C66yWXw9vILRYtPja6wWl3fNYbP43HuE0WLG+X1MFqeuf2azWLT1C7tFxzJGBx6P 378mMXrsnHWX3ePOtT1sHpuX1HtcOdHE6tG3ZRWjx+dNcgHsUVw2Kak5mWWpRfp2CVwZTa9X sBb83MFY8W73evYGxluTGbsYOTkkBEwkbp5oZ4awxSQu3FvP1sXIxSEksIJR4tDvqUwwRQ/n vmSHSMxilDh78wGU08ok8eXRZLAqNgFdiSfv5zKDJEQEWhkllu3/zwTiMAscYJTYse4V2EJh AW+JCxtagRIcHCwCqhI314uChHkFPCQmzjgLFpYQkJNY2lwLEuYU8JTYsfQIWFgIqOTdCXWQ iRICl9glnvQeZAWpYREQkPg2+RALRKusxKYDUN9IShxccYNlAqPwAkaGVYyiqQXJBcVJ6UWm esWJucWleel6yfm5mxiBsXL637OJOxjvH7A+xCjAwajEw9v41zNMiDWxrLgy9xCjKdCGicxS osn5wIjMK4k3NDYzsjA1MTU2Mrc0UxLn1ZH+GSwkkJ5YkpqdmlqQWhRfVJqTWnyIkYmDU6qB MXiK/8KiBcVMyqfDDJgfBf85e/+tvSQj5zamcKsJIWVB5645HcxfvdrsRJ72l5Iqy9mKy8se pMmJ7lSR8udxXnF9xyKet7YdP9QOTOt1MBax8qlKeaC/cMEsKZPdHvEeqSreuxaI9rn3fW6y Npp+QPT0KrEk4YuX/Ow3OHL4PFJ6/OZFM4OEEktxRqKhFnNRcSIAv73EVJACAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrFIsWRmVeSWpSXmKPExsVy+t9jQV2do15hBp8e81p8XP2SzeLvpGPs Fq9fGFr0LrjKZvH18ApGi02Pr7FaXN41h83ic+8RRosZ5/cxWZy6/pnNYtHWL+wWHcsYHXg8 fv+axOixc9Zddo871/aweWxeUu9x5UQTq0ffllWMHp83yQWwRzUw2mSkJqakFimk5iXnp2Tm pdsqeQfHO8ebmhkY6hpaWpgrKeQl5qbaKrn4BOi6ZeYA3amkUJaYUwoUCkgsLlbSt8M0ITTE TdcCpjFC1zckCK7HyAANJKxhzGh6vYK14OcOxop3u9ezNzDemszYxcjJISFgIvFw7kt2CFtM 4sK99WxdjFwcQgKzGCXO3nzADuG0Mkl8eTSZCaSKTUBX4sn7ucwgCRGBVkaJZfv/M4E4zAIH GCV2rHsFNldYwFviwoZWoAQHB4uAqsTN9aIgYV4BD4mJM86ChSUE5CSWNteChDkFPCV2LD0C FhYCKnl3Qn0CI+8CRoZVjBKpBckFxUnpuYZ5qeV6xYm5xaV56XrJ+bmbGMHx+ExqB+PBXe6H GAU4GJV4eBv+eoYJsSaWFVfmHmKU4GBWEuF9csgrTIg3JbGyKrUoP76oNCe1+BCjKdBVE5ml RJPzgakiryTe0NjE3NTY1NLEwsTMUkmcV9/TKExIID2xJDU7NbUgtQimj4mDU6qBcbbUiRST rZq/vXxe90VseMvfk9ww6cQ9Pze95y3eIXn/p+RpVW6ZypKp8NrszS8Dj13MhcbCG3SC7plv 2ikRn8U8YckHowMlM6RrLieyf3bMefVwH5PWzSfpz6tW3jwacaP0nVGk9jS2k28co07p+LL0 t3K+ynrGcC1uXcaLrSvYrM+KCxhtVWIpzkg01GIuKk4EAKSvudXdAgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY, UPPERCASE_50_75 autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch splits up mach-exynos/pmu.c file, and moves exynos4210, exynos4412 and exynos4212 PMU configuration data and functions handing data into a common exynos4 SoC specific PMU file mach-exynos/exynos4-pmu.c. Signed-off-by: Pankaj Dubey Reviewed-by: Krzysztof Kozlowski --- arch/arm/mach-exynos/Makefile | 2 +- arch/arm/mach-exynos/exynos-pmu.h | 3 + arch/arm/mach-exynos/exynos4-pmu.c | 222 +++++++++++++++++++++++++++++++++++++ arch/arm/mach-exynos/pmu.c | 207 ---------------------------------- 4 files changed, 226 insertions(+), 208 deletions(-) create mode 100644 arch/arm/mach-exynos/exynos4-pmu.c diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile index e869f86..8969683 100644 --- a/arch/arm/mach-exynos/Makefile +++ b/arch/arm/mach-exynos/Makefile @@ -9,7 +9,7 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) += -I$(srctree)/$(src)/include -I$(srctree) # Core -obj-$(CONFIG_ARCH_EXYNOS) += exynos.o pmu.o exynos-smc.o firmware.o exynos3250-pmu.o +obj-$(CONFIG_ARCH_EXYNOS) += exynos.o pmu.o exynos-smc.o firmware.o exynos3250-pmu.o exynos4-pmu.o obj-$(CONFIG_EXYNOS_CPU_SUSPEND) += pm.o sleep.o obj-$(CONFIG_PM_SLEEP) += suspend.o diff --git a/arch/arm/mach-exynos/exynos-pmu.h b/arch/arm/mach-exynos/exynos-pmu.h index 5d09fa3..3d21aad 100644 --- a/arch/arm/mach-exynos/exynos-pmu.h +++ b/arch/arm/mach-exynos/exynos-pmu.h @@ -33,6 +33,9 @@ struct exynos_pmu_data { extern void __iomem *pmu_base_addr; /* list of all exported SoC specific data */ extern const struct exynos_pmu_data exynos3250_pmu_data; +extern const struct exynos_pmu_data exynos4210_pmu_data; +extern const struct exynos_pmu_data exynos4212_pmu_data; +extern const struct exynos_pmu_data exynos4412_pmu_data; extern void pmu_raw_writel(u32 val, u32 offset); extern u32 pmu_raw_readl(u32 offset); diff --git a/arch/arm/mach-exynos/exynos4-pmu.c b/arch/arm/mach-exynos/exynos4-pmu.c new file mode 100644 index 0000000..bc4fa73 --- /dev/null +++ b/arch/arm/mach-exynos/exynos4-pmu.c @@ -0,0 +1,222 @@ +/* + * Copyright (c) 2011-2015 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * EXYNOS4 - CPU PMU(Power Management Unit) support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include + +#include "exynos-pmu.h" + +static const struct exynos_pmu_conf exynos4210_pmu_config[] = { + /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */ + { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } }, + { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } }, + { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } }, + { S5P_ARM_CORE1_LOWPWR, { 0x0, 0x0, 0x2 } }, + { S5P_DIS_IRQ_CORE1, { 0x0, 0x0, 0x0 } }, + { S5P_DIS_IRQ_CENTRAL1, { 0x0, 0x0, 0x0 } }, + { S5P_ARM_COMMON_LOWPWR, { 0x0, 0x0, 0x2 } }, + { S5P_L2_0_LOWPWR, { 0x2, 0x2, 0x3 } }, + { S5P_L2_1_LOWPWR, { 0x2, 0x2, 0x3 } }, + { S5P_CMU_ACLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_SCLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_RESET_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_APLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_MPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_VPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_EPLL_SYSCLK_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_CMU_RESET_GPSALIVE_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_CMU_CLKSTOP_CAM_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_CMU_CLKSTOP_TV_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_CMU_CLKSTOP_MFC_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_CMU_CLKSTOP_G3D_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_CMU_CLKSTOP_LCD0_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_CMU_CLKSTOP_LCD1_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_CMU_CLKSTOP_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_CMU_CLKSTOP_GPS_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_CMU_RESET_CAM_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_CMU_RESET_TV_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_CMU_RESET_MFC_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_CMU_RESET_G3D_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_CMU_RESET_LCD0_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_CMU_RESET_LCD1_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_CMU_RESET_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_CMU_RESET_GPS_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_TOP_BUS_LOWPWR, { 0x3, 0x0, 0x0 } }, + { S5P_TOP_RETENTION_LOWPWR, { 0x1, 0x0, 0x1 } }, + { S5P_TOP_PWR_LOWPWR, { 0x3, 0x0, 0x3 } }, + { S5P_LOGIC_RESET_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_ONENAND_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, + { S5P_MODIMIF_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, + { S5P_G2D_ACP_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, + { S5P_USBOTG_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, + { S5P_HSMMC_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, + { S5P_CSSYS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, + { S5P_SECSS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, + { S5P_PCIE_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, + { S5P_SATA_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, + { S5P_PAD_RETENTION_DRAM_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_PAD_RETENTION_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_PAD_RETENTION_GPIO_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_PAD_RETENTION_UART_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_PAD_RETENTION_MMCA_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_PAD_RETENTION_MMCB_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_PAD_RETENTION_EBIA_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_PAD_RETENTION_EBIB_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_PAD_RETENTION_ISOLATION_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_PAD_RETENTION_ALV_SEL_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_XUSBXTI_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_XXTI_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_EXT_REGULATOR_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_GPIO_MODE_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_GPIO_MODE_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_CAM_LOWPWR, { 0x7, 0x0, 0x0 } }, + { S5P_TV_LOWPWR, { 0x7, 0x0, 0x0 } }, + { S5P_MFC_LOWPWR, { 0x7, 0x0, 0x0 } }, + { S5P_G3D_LOWPWR, { 0x7, 0x0, 0x0 } }, + { S5P_LCD0_LOWPWR, { 0x7, 0x0, 0x0 } }, + { S5P_LCD1_LOWPWR, { 0x7, 0x0, 0x0 } }, + { S5P_MAUDIO_LOWPWR, { 0x7, 0x7, 0x0 } }, + { S5P_GPS_LOWPWR, { 0x7, 0x0, 0x0 } }, + { S5P_GPS_ALIVE_LOWPWR, { 0x7, 0x0, 0x0 } }, + { PMU_TABLE_END,}, +}; + +static const struct exynos_pmu_conf exynos4x12_pmu_config[] = { + { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } }, + { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } }, + { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } }, + { S5P_ARM_CORE1_LOWPWR, { 0x0, 0x0, 0x2 } }, + { S5P_DIS_IRQ_CORE1, { 0x0, 0x0, 0x0 } }, + { S5P_DIS_IRQ_CENTRAL1, { 0x0, 0x0, 0x0 } }, + { S5P_ISP_ARM_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR, { 0x0, 0x0, 0x0 } }, + { S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR, { 0x0, 0x0, 0x0 } }, + { S5P_ARM_COMMON_LOWPWR, { 0x0, 0x0, 0x2 } }, + { S5P_L2_0_LOWPWR, { 0x0, 0x0, 0x3 } }, + /* XXX_OPTION register should be set other field */ + { S5P_ARM_L2_0_OPTION, { 0x10, 0x10, 0x0 } }, + { S5P_L2_1_LOWPWR, { 0x0, 0x0, 0x3 } }, + { S5P_ARM_L2_1_OPTION, { 0x10, 0x10, 0x0 } }, + { S5P_CMU_ACLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_SCLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_RESET_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_DRAM_FREQ_DOWN_LOWPWR, { 0x1, 0x1, 0x1 } }, + { S5P_DDRPHY_DLLOFF_LOWPWR, { 0x1, 0x1, 0x1 } }, + { S5P_LPDDR_PHY_DLL_LOCK_LOWPWR, { 0x1, 0x1, 0x1 } }, + { S5P_CMU_ACLKSTOP_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_SCLKSTOP_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_RESET_COREBLK_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_APLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_MPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_VPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_EPLL_SYSCLK_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_MPLLUSER_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_RESET_GPSALIVE_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_CLKSTOP_CAM_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_CLKSTOP_TV_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_CLKSTOP_MFC_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_CLKSTOP_G3D_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_CLKSTOP_LCD0_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_CLKSTOP_ISP_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_CLKSTOP_MAUDIO_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_CLKSTOP_GPS_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_RESET_CAM_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_RESET_TV_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_RESET_MFC_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_RESET_G3D_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_RESET_LCD0_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_RESET_ISP_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_RESET_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_CMU_RESET_GPS_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_TOP_BUS_LOWPWR, { 0x3, 0x0, 0x0 } }, + { S5P_TOP_RETENTION_LOWPWR, { 0x1, 0x0, 0x1 } }, + { S5P_TOP_PWR_LOWPWR, { 0x3, 0x0, 0x3 } }, + { S5P_TOP_BUS_COREBLK_LOWPWR, { 0x3, 0x0, 0x0 } }, + { S5P_TOP_RETENTION_COREBLK_LOWPWR, { 0x1, 0x0, 0x1 } }, + { S5P_TOP_PWR_COREBLK_LOWPWR, { 0x3, 0x0, 0x3 } }, + { S5P_LOGIC_RESET_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_OSCCLK_GATE_LOWPWR, { 0x1, 0x0, 0x1 } }, + { S5P_LOGIC_RESET_COREBLK_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_OSCCLK_GATE_COREBLK_LOWPWR, { 0x1, 0x0, 0x1 } }, + { S5P_ONENAND_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, + { S5P_ONENAND_MEM_OPTION, { 0x10, 0x10, 0x0 } }, + { S5P_HSI_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, + { S5P_HSI_MEM_OPTION, { 0x10, 0x10, 0x0 } }, + { S5P_G2D_ACP_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, + { S5P_G2D_ACP_MEM_OPTION, { 0x10, 0x10, 0x0 } }, + { S5P_USBOTG_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, + { S5P_USBOTG_MEM_OPTION, { 0x10, 0x10, 0x0 } }, + { S5P_HSMMC_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, + { S5P_HSMMC_MEM_OPTION, { 0x10, 0x10, 0x0 } }, + { S5P_CSSYS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, + { S5P_CSSYS_MEM_OPTION, { 0x10, 0x10, 0x0 } }, + { S5P_SECSS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, + { S5P_SECSS_MEM_OPTION, { 0x10, 0x10, 0x0 } }, + { S5P_ROTATOR_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, + { S5P_ROTATOR_MEM_OPTION, { 0x10, 0x10, 0x0 } }, + { S5P_PAD_RETENTION_DRAM_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_PAD_RETENTION_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_PAD_RETENTION_GPIO_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_PAD_RETENTION_UART_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_PAD_RETENTION_MMCA_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_PAD_RETENTION_MMCB_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_PAD_RETENTION_EBIA_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_PAD_RETENTION_EBIB_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_PAD_RETENTION_ISOLATION_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_PAD_ISOLATION_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_PAD_RETENTION_ALV_SEL_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_XUSBXTI_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_XXTI_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_EXT_REGULATOR_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_GPIO_MODE_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_GPIO_MODE_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_GPIO_MODE_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } }, + { S5P_TOP_ASB_RESET_LOWPWR, { 0x1, 0x1, 0x1 } }, + { S5P_TOP_ASB_ISOLATION_LOWPWR, { 0x1, 0x0, 0x1 } }, + { S5P_CAM_LOWPWR, { 0x7, 0x0, 0x0 } }, + { S5P_TV_LOWPWR, { 0x7, 0x0, 0x0 } }, + { S5P_MFC_LOWPWR, { 0x7, 0x0, 0x0 } }, + { S5P_G3D_LOWPWR, { 0x7, 0x0, 0x0 } }, + { S5P_LCD0_LOWPWR, { 0x7, 0x0, 0x0 } }, + { S5P_ISP_LOWPWR, { 0x7, 0x0, 0x0 } }, + { S5P_MAUDIO_LOWPWR, { 0x7, 0x7, 0x0 } }, + { S5P_GPS_LOWPWR, { 0x7, 0x0, 0x0 } }, + { S5P_GPS_ALIVE_LOWPWR, { 0x7, 0x0, 0x0 } }, + { S5P_CMU_SYSCLK_ISP_LOWPWR, { 0x1, 0x0, 0x0 } }, + { S5P_CMU_SYSCLK_GPS_LOWPWR, { 0x1, 0x0, 0x0 } }, + { PMU_TABLE_END,}, +}; + +static const struct exynos_pmu_conf exynos4412_pmu_config[] = { + { S5P_ARM_CORE2_LOWPWR, { 0x0, 0x0, 0x2 } }, + { S5P_DIS_IRQ_CORE2, { 0x0, 0x0, 0x0 } }, + { S5P_DIS_IRQ_CENTRAL2, { 0x0, 0x0, 0x0 } }, + { S5P_ARM_CORE3_LOWPWR, { 0x0, 0x0, 0x2 } }, + { S5P_DIS_IRQ_CORE3, { 0x0, 0x0, 0x0 } }, + { S5P_DIS_IRQ_CENTRAL3, { 0x0, 0x0, 0x0 } }, + { PMU_TABLE_END,}, +}; + +const struct exynos_pmu_data exynos4210_pmu_data = { + .pmu_config = exynos4210_pmu_config, +}; + +const struct exynos_pmu_data exynos4212_pmu_data = { + .pmu_config = exynos4x12_pmu_config, +}; + +const struct exynos_pmu_data exynos4412_pmu_data = { + .pmu_config = exynos4x12_pmu_config, + .pmu_config_extra = exynos4412_pmu_config, +}; diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c index c594804..73a5030 100644 --- a/arch/arm/mach-exynos/pmu.c +++ b/arch/arm/mach-exynos/pmu.c @@ -41,200 +41,6 @@ u32 pmu_raw_readl(u32 offset) return readl_relaxed(pmu_base_addr + offset); } -static const struct exynos_pmu_conf exynos4210_pmu_config[] = { - /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */ - { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } }, - { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } }, - { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } }, - { S5P_ARM_CORE1_LOWPWR, { 0x0, 0x0, 0x2 } }, - { S5P_DIS_IRQ_CORE1, { 0x0, 0x0, 0x0 } }, - { S5P_DIS_IRQ_CENTRAL1, { 0x0, 0x0, 0x0 } }, - { S5P_ARM_COMMON_LOWPWR, { 0x0, 0x0, 0x2 } }, - { S5P_L2_0_LOWPWR, { 0x2, 0x2, 0x3 } }, - { S5P_L2_1_LOWPWR, { 0x2, 0x2, 0x3 } }, - { S5P_CMU_ACLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_SCLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_RESET_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_APLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_MPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_VPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_EPLL_SYSCLK_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_RESET_GPSALIVE_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_CLKSTOP_CAM_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_CLKSTOP_TV_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_CLKSTOP_MFC_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_CLKSTOP_G3D_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_CLKSTOP_LCD0_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_CLKSTOP_LCD1_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_CLKSTOP_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_CLKSTOP_GPS_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_RESET_CAM_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_RESET_TV_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_RESET_MFC_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_RESET_G3D_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_RESET_LCD0_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_RESET_LCD1_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_RESET_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_RESET_GPS_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_TOP_BUS_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_TOP_RETENTION_LOWPWR, { 0x1, 0x0, 0x1 } }, - { S5P_TOP_PWR_LOWPWR, { 0x3, 0x0, 0x3 } }, - { S5P_LOGIC_RESET_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_ONENAND_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_MODIMIF_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_G2D_ACP_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_USBOTG_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_HSMMC_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_CSSYS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_SECSS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_PCIE_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_SATA_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_DRAM_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_PAD_RETENTION_GPIO_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_UART_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_MMCA_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_MMCB_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_EBIA_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_EBIB_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_ISOLATION_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_ALV_SEL_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_XUSBXTI_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_XXTI_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_EXT_REGULATOR_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_GPIO_MODE_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_GPIO_MODE_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CAM_LOWPWR, { 0x7, 0x0, 0x0 } }, - { S5P_TV_LOWPWR, { 0x7, 0x0, 0x0 } }, - { S5P_MFC_LOWPWR, { 0x7, 0x0, 0x0 } }, - { S5P_G3D_LOWPWR, { 0x7, 0x0, 0x0 } }, - { S5P_LCD0_LOWPWR, { 0x7, 0x0, 0x0 } }, - { S5P_LCD1_LOWPWR, { 0x7, 0x0, 0x0 } }, - { S5P_MAUDIO_LOWPWR, { 0x7, 0x7, 0x0 } }, - { S5P_GPS_LOWPWR, { 0x7, 0x0, 0x0 } }, - { S5P_GPS_ALIVE_LOWPWR, { 0x7, 0x0, 0x0 } }, - { PMU_TABLE_END,}, -}; - -static const struct exynos_pmu_conf exynos4x12_pmu_config[] = { - { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } }, - { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } }, - { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } }, - { S5P_ARM_CORE1_LOWPWR, { 0x0, 0x0, 0x2 } }, - { S5P_DIS_IRQ_CORE1, { 0x0, 0x0, 0x0 } }, - { S5P_DIS_IRQ_CENTRAL1, { 0x0, 0x0, 0x0 } }, - { S5P_ISP_ARM_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR, { 0x0, 0x0, 0x0 } }, - { S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR, { 0x0, 0x0, 0x0 } }, - { S5P_ARM_COMMON_LOWPWR, { 0x0, 0x0, 0x2 } }, - { S5P_L2_0_LOWPWR, { 0x0, 0x0, 0x3 } }, - /* XXX_OPTION register should be set other field */ - { S5P_ARM_L2_0_OPTION, { 0x10, 0x10, 0x0 } }, - { S5P_L2_1_LOWPWR, { 0x0, 0x0, 0x3 } }, - { S5P_ARM_L2_1_OPTION, { 0x10, 0x10, 0x0 } }, - { S5P_CMU_ACLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_SCLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_RESET_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_DRAM_FREQ_DOWN_LOWPWR, { 0x1, 0x1, 0x1 } }, - { S5P_DDRPHY_DLLOFF_LOWPWR, { 0x1, 0x1, 0x1 } }, - { S5P_LPDDR_PHY_DLL_LOCK_LOWPWR, { 0x1, 0x1, 0x1 } }, - { S5P_CMU_ACLKSTOP_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_SCLKSTOP_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_RESET_COREBLK_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_APLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_MPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_VPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_EPLL_SYSCLK_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_MPLLUSER_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_RESET_GPSALIVE_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_CLKSTOP_CAM_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_CLKSTOP_TV_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_CLKSTOP_MFC_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_CLKSTOP_G3D_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_CLKSTOP_LCD0_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_CLKSTOP_ISP_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_CLKSTOP_MAUDIO_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_CLKSTOP_GPS_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_RESET_CAM_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_RESET_TV_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_RESET_MFC_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_RESET_G3D_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_RESET_LCD0_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_RESET_ISP_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_RESET_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_RESET_GPS_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_TOP_BUS_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_TOP_RETENTION_LOWPWR, { 0x1, 0x0, 0x1 } }, - { S5P_TOP_PWR_LOWPWR, { 0x3, 0x0, 0x3 } }, - { S5P_TOP_BUS_COREBLK_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_TOP_RETENTION_COREBLK_LOWPWR, { 0x1, 0x0, 0x1 } }, - { S5P_TOP_PWR_COREBLK_LOWPWR, { 0x3, 0x0, 0x3 } }, - { S5P_LOGIC_RESET_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_OSCCLK_GATE_LOWPWR, { 0x1, 0x0, 0x1 } }, - { S5P_LOGIC_RESET_COREBLK_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_OSCCLK_GATE_COREBLK_LOWPWR, { 0x1, 0x0, 0x1 } }, - { S5P_ONENAND_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_ONENAND_MEM_OPTION, { 0x10, 0x10, 0x0 } }, - { S5P_HSI_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_HSI_MEM_OPTION, { 0x10, 0x10, 0x0 } }, - { S5P_G2D_ACP_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_G2D_ACP_MEM_OPTION, { 0x10, 0x10, 0x0 } }, - { S5P_USBOTG_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_USBOTG_MEM_OPTION, { 0x10, 0x10, 0x0 } }, - { S5P_HSMMC_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_HSMMC_MEM_OPTION, { 0x10, 0x10, 0x0 } }, - { S5P_CSSYS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_CSSYS_MEM_OPTION, { 0x10, 0x10, 0x0 } }, - { S5P_SECSS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_SECSS_MEM_OPTION, { 0x10, 0x10, 0x0 } }, - { S5P_ROTATOR_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_ROTATOR_MEM_OPTION, { 0x10, 0x10, 0x0 } }, - { S5P_PAD_RETENTION_DRAM_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_PAD_RETENTION_GPIO_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_UART_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_MMCA_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_MMCB_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_EBIA_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_EBIB_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR,{ 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_ISOLATION_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_ISOLATION_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_ALV_SEL_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_XUSBXTI_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_XXTI_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_EXT_REGULATOR_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_GPIO_MODE_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_GPIO_MODE_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_GPIO_MODE_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_TOP_ASB_RESET_LOWPWR, { 0x1, 0x1, 0x1 } }, - { S5P_TOP_ASB_ISOLATION_LOWPWR, { 0x1, 0x0, 0x1 } }, - { S5P_CAM_LOWPWR, { 0x7, 0x0, 0x0 } }, - { S5P_TV_LOWPWR, { 0x7, 0x0, 0x0 } }, - { S5P_MFC_LOWPWR, { 0x7, 0x0, 0x0 } }, - { S5P_G3D_LOWPWR, { 0x7, 0x0, 0x0 } }, - { S5P_LCD0_LOWPWR, { 0x7, 0x0, 0x0 } }, - { S5P_ISP_LOWPWR, { 0x7, 0x0, 0x0 } }, - { S5P_MAUDIO_LOWPWR, { 0x7, 0x7, 0x0 } }, - { S5P_GPS_LOWPWR, { 0x7, 0x0, 0x0 } }, - { S5P_GPS_ALIVE_LOWPWR, { 0x7, 0x0, 0x0 } }, - { S5P_CMU_SYSCLK_ISP_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_SYSCLK_GPS_LOWPWR, { 0x1, 0x0, 0x0 } }, - { PMU_TABLE_END,}, -}; - -static const struct exynos_pmu_conf exynos4412_pmu_config[] = { - { S5P_ARM_CORE2_LOWPWR, { 0x0, 0x0, 0x2 } }, - { S5P_DIS_IRQ_CORE2, { 0x0, 0x0, 0x0 } }, - { S5P_DIS_IRQ_CENTRAL2, { 0x0, 0x0, 0x0 } }, - { S5P_ARM_CORE3_LOWPWR, { 0x0, 0x0, 0x2 } }, - { S5P_DIS_IRQ_CORE3, { 0x0, 0x0, 0x0 } }, - { S5P_DIS_IRQ_CENTRAL3, { 0x0, 0x0, 0x0 } }, - { PMU_TABLE_END,}, -}; - static const struct exynos_pmu_conf exynos5250_pmu_config[] = { /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */ { EXYNOS5_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x2} }, @@ -718,19 +524,6 @@ static int pmu_restart_notify(struct notifier_block *this, return NOTIFY_DONE; } -static const struct exynos_pmu_data exynos4210_pmu_data = { - .pmu_config = exynos4210_pmu_config, -}; - -static const struct exynos_pmu_data exynos4212_pmu_data = { - .pmu_config = exynos4x12_pmu_config, -}; - -static const struct exynos_pmu_data exynos4412_pmu_data = { - .pmu_config = exynos4x12_pmu_config, - .pmu_config_extra = exynos4412_pmu_config, -}; - static const struct exynos_pmu_data exynos5250_pmu_data = { .pmu_config = exynos5250_pmu_config, .pmu_init = exynos5250_pmu_init,