From patchwork Thu Nov 26 13:47:33 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chanwoo Choi X-Patchwork-Id: 7706951 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id D59C3BF90C for ; Thu, 26 Nov 2015 13:49:48 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 9DB8F207A1 for ; Thu, 26 Nov 2015 13:49:44 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 620B920797 for ; Thu, 26 Nov 2015 13:49:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752208AbbKZNtk (ORCPT ); Thu, 26 Nov 2015 08:49:40 -0500 Received: from mailout4.samsung.com ([203.254.224.34]:40834 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752257AbbKZNr4 (ORCPT ); Thu, 26 Nov 2015 08:47:56 -0500 Received: from epcpsbgr3.samsung.com (u143.gpu120.samsung.co.kr [203.254.230.143]) by mailout4.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NYF02U9FCZHHP40@mailout4.samsung.com>; Thu, 26 Nov 2015 22:47:41 +0900 (KST) Received: from epcpsbgm2new.samsung.com ( [172.20.52.112]) by epcpsbgr3.samsung.com (EPCPMTA) with SMTP id 4E.1A.30395.D7D07565; Thu, 26 Nov 2015 22:47:41 +0900 (KST) X-AuditID: cbfee68f-f79666d0000076bb-b6-56570d7d6d5d Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2new.samsung.com (EPCPMTA) with SMTP id 04.AF.00996.D7D07565; Thu, 26 Nov 2015 22:47:41 +0900 (KST) Received: from chan.10.32.193.11 ([10.252.81.195]) by mmp1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NYF00D4UCZGTXL0@mmp1.samsung.com>; Thu, 26 Nov 2015 22:47:41 +0900 (KST) From: Chanwoo Choi To: myungjoo.ham@samsung.com, kyungmin.park@samsung.com, kgene@kernel.org, k.kozlowski@samsung.com Cc: robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux@arm.linux.org.uk, tjakobi@math.uni-bielefeld.de, cw00.choi@samsung.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org Subject: [RFC PATCH 09/15] PM / devfreq: exynos: Update documentation for bus devices using passive governor Date: Thu, 26 Nov 2015 22:47:33 +0900 Message-id: <1448545659-32287-10-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1448545659-32287-1-git-send-email-cw00.choi@samsung.com> References: <1448545659-32287-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprKIsWRmVeSWpSXmKPExsWyRsSkQLeWNzzM4P4kbYvrX56zWsw/co7V ov/NQlaLc69WMlq8fmFo0f/4NbPF2aY37BaXd81hs/jce4TRYsb5fUwWty/zWiy9fhHIaFzB ZjFh+loWi9a9R9gt2lZ/YHUQ8Fgzbw2jR0tzD5vH5b5eJo+Vy7+weWxa1cnm8e8Yu0ffllWM Hp83yQVwRHHZpKTmZJalFunbJXBlzF59gL1gj23F9vl3WBoYT+h3MXJwSAiYSMz/oNfFyAlk iklcuLeerYuRi0NIYAWjxJWb81khEiYSjT0fGSESSxklPjU/h3K+MEqcPXuBDaSKTUBLYv+L G2C2iECKxN+bs8GKmAUOMUmceXeECSQhLJAnsfvNJTCbRUBVYveZi8wgNq+Am8TiRU+h1slJ fNjziB3E5gSKn7oyiRHEFhJwlZj8sQfsPgmBr+wSs9/cYIcYJCDxbfIhFoh/ZCU2HWCGmCMp cXDFDZYJjMILGBlWMYqmFiQXFCelFxnrFSfmFpfmpesl5+duYgTG1ul/z/p3MN49YH2IUYCD UYmHt8A2LEyINbGsuDL3EKMp0IaJzFKiyfnACM4riTc0NjOyMDUxNTYytzRTEuddKPUzWEgg PbEkNTs1tSC1KL6oNCe1+BAjEwenVAOjF8fxC0ddPHSTebNK8nyephg/q7sae22v1MHUI6Z9 UXopHV+WlApdt39gUxPG5jRPkcNz1Y11bHnn/VRnHFYzuFDId/L5FLaSPQd2lkf4FaR1TZiW cGjv4cl1r69lTojs+7tDp6ZvxffcmXmHzcu9/PS05r+ccn/Z4ZSA++GCOs9e9k2t2n5TiaU4 I9FQi7moOBEAKUqS26gCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrMIsWRmVeSWpSXmKPExsVy+t9jAd1a3vAwg2dflC2uf3nOajH/yDlW i/43C1ktzr1ayWjx+oWhRf/j18wWZ5vesFtc3jWHzeJz7xFGixnn9zFZ3L7Ma7H0+kUgo3EF m8WE6WtZLFr3HmG3aFv9gdVBwGPNvDWMHi3NPWwel/t6mTxWLv/C5rFpVSebx79j7B59W1Yx enzeJBfAEdXAaJORmpiSWqSQmpecn5KZl26r5B0c7xxvamZgqGtoaWGupJCXmJtqq+TiE6Dr lpkD9ICSQlliTilQKCCxuFhJ3w7ThNAQN10LmMYIXd+QILgeIwM0kLCGMWP26gPsBXtsK7bP v8PSwHhCv4uRk0NCwESisecjI4QtJnHh3nq2LkYuDiGBpYwSn5qfM0I4Xxglzp69wAZSxSag JbH/xQ0wW0QgReLvzdlgRcwCh5gkzrw7wgSSEBbIk9j95hKYzSKgKrH7zEVmEJtXwE1i8aKn rBDr5CQ+7HnEDmJzAsVPXZkEdoaQgKvE5I89bBMYeRcwMqxilEgtSC4oTkrPNcpLLdcrTswt Ls1L10vOz93ECI7gZ9I7GA/vcj/EKMDBqMTDW2AbFibEmlhWXJl7iFGCg1lJhPcWS3iYEG9K YmVValF+fFFpTmrxIUZToMMmMkuJJucDk0teSbyhsYmZkaWRuaGFkbG5kjjvhf1+YUIC6Ykl qdmpqQWpRTB9TBycUg2MdeE7Hz7O+HLmkr5D4nn3R29uRjxb/u15oXqjWM/p20mvAwwMd59W O8f/7ar0DGHOvjXf1+yZcTR00c5JC7kv+uQFJoa73Iy1nfPKb1//qitTmRjO3DtaVZ49Z0Hk 0tcC9iv/BH1bmbdFesmFIAb7DotEw/Cfd2bc/leavW6u/rlz22N7rLTrHimxFGckGmoxFxUn AgD90BEA9gIAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch updates the documentation for passive bus devices and adds the detailed example of Exynos3250. Signed-off-by: Chanwoo Choi --- .../devicetree/bindings/devfreq/exynos-bus.txt | 226 ++++++++++++++++++++- 1 file changed, 223 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt index 5d90623bd173..c4a6fe30075e 100644 --- a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt +++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt @@ -12,18 +12,23 @@ SoC has the different sub-blocks. So, this difference should be specified in devicetree file instead of each device driver. In result, this driver is able to support the bus frequency for all Exynos SoCs. -Required properties for bus device: +Required properties for all bus devices: - compatible: Should be "samsung,exynos-bus". - clock-names : the name of clock used by the bus, "bus". - clocks : phandles for clock specified in "clock-names" property. - #clock-cells: should be 1. - operating-points-v2: the OPP table including frequency/voltage information to support DVFS (Dynamic Voltage/Frequency Scaling) feature. + +Required properties for only parent bus device: - vdd-supply: the regulator to provide the buses with the voltage. - devfreq-events: the devfreq-event device to monitor the curret utilization of buses. -Optional properties for bus device: +Required properties for only passive bus device: +- devfreq: the parent bus device. + +Optional properties for only parent bus device: - exynos,saturation-ratio: the percentage value which is used to calibrate the performance count againt total cycle count. @@ -32,7 +37,19 @@ Example1: power line (regulator). The MIF (Memory Interface) AXI bus is used to transfer data between DRAM and CPU and uses the VDD_MIF regualtor. - - power line(VDD_MIF) --> bus for DMC block (dmc clock) + - MIF (Memory Interface) block + : VDD_MIF |--- DMC + + - INT (Internal) block + : VDD_INT |--- LEFTBUS |--- PERIL + | (parent) |--- MFC + | |--- G3D + | + |--- RIGHTBUS |--- FSYS + |--- LCD0 + |--- PERIR + |--- ISP + |--- CAM - MIF bus's frequency/voltage table ----------------------- @@ -45,6 +62,20 @@ Example1: |L5| 400000 |875000 | ----------------------- + - INT bus's frequency/voltage table + ----------------------------------------------------------------------- + |Lv| Freq | Voltage | + ----------------------------------------------------------------------- + | |LEFTBUS|RIGHTBUS|LCD0 |FSYS |MCUISP |ISP |PERIL |VDD_INT | + | |*parent|passive |passive|passive|passive|passive|passive| | + ----------------------------------------------------------------------- + |L1|50000 |50000 |50000 |50000 |50000 |50000 |50000 |900000 | + |L2|80000 |80000 |80000 |80000 |80000 |80000 |80000 |900000 | + |L3|100000 |100000 |100000 |100000 |100000 |100000 |100000 |1000000 | + |L4|133000 |133000 |133000 |133000 |200000 |200000 | |1000000 | + |L5|200000 |200000 |200000 |200000 |400000 |300000 | |1000000 | + ----------------------------------------------------------------------- + Example2 : The bus of DMC block in exynos3250.dtsi are listed below: @@ -82,6 +113,159 @@ Example2 : }; }; + bus_leftbus: bus_leftbus { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_GDL>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_rightbus: bus_rightbus { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_GDR>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_lcd0: bus_lcd0 { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_160>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_fsys: bus_fsys { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_200>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_mcuisp: bus_mcuisp { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>; + clock-names = "bus"; + operating-points-v2 = <&bus_mcuisp_opp_table>; + status = "disabled"; + }; + + bus_isp: bus_isp { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_266>; + clock-names = "bus"; + operating-points-v2 = <&bus_isp_opp_table>; + status = "disabled"; + }; + + bus_peril: bus_perir { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_100>; + clock-names = "bus"; + operating-points-v2 = <&bus_peril_opp_table>; + status = "disabled"; + }; + + bus_leftbus_opp_table: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <50000000>; + opp-microvolt = <900000>; + }; + opp01 { + opp-hz = /bits/ 64 <80000000>; + opp-microvolt = <900000>; + }; + opp02 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <1000000>; + }; + opp03 { + opp-hz = /bits/ 64 <133000000>; + opp-microvolt = <1000000>; + }; + opp04 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1000000>; + }; + }; + + bus_mcuisp_opp_table: opp_table2 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <50000000>; + opp-microvolt = <900000>; + }; + opp01 { + opp-hz = /bits/ 64 <80000000>; + opp-microvolt = <900000>; + }; + opp02 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <1000000>; + }; + opp03 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1000000>; + }; + opp04 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1000000>; + }; + }; + + bus_isp_opp_table: opp_table3 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <50000000>; + opp-microvolt = <900000>; + }; + opp01 { + opp-hz = /bits/ 64 <80000000>; + opp-microvolt = <900000>; + }; + opp02 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <1000000>; + }; + opp03 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1000000>; + }; + opp04 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <1000000>; + }; + }; + + bus_peril_opp_table: opp_table4 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <50000000>; + opp-microvolt = <900000>; + }; + opp01 { + opp-hz = /bits/ 64 <80000000>; + opp-microvolt = <900000>; + }; + opp02 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <1000000>; + }; + }; + + Usage case to handle the frequency and voltage of bus on runtime in exynos3250-rinato.dts are listed below: @@ -90,3 +274,39 @@ Example2 : vdd-supply = <&buck1_reg>; /* VDD_MIF */ status = "okay"; }; + + &bus_leftbus { + devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>; + vdd-supply = <&buck3_reg>; + status = "okay"; + }; + + &bus_rightbus { + devfreq = <&bus_leftbus>; + status = "okay"; + }; + + &bus_lcd0 { + devfreq = <&bus_leftbus>; + status = "okay"; + }; + + &bus_fsys { + devfreq = <&bus_leftbus>; + status = "okay"; + }; + + &bus_mcuisp { + devfreq = <&bus_leftbus>; + status = "okay"; + }; + + &bus_isp { + devfreq = <&bus_leftbus>; + status = "okay"; + }; + + &bus_peril { + devfreq = <&bus_leftbus>; + status = "okay"; + };