From patchwork Thu Nov 26 13:47:26 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chanwoo Choi X-Patchwork-Id: 7707071 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id DCD559F2EC for ; Thu, 26 Nov 2015 13:51:14 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id C9A6D204FB for ; Thu, 26 Nov 2015 13:51:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BE42D2045E for ; Thu, 26 Nov 2015 13:51:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752119AbbKZNrt (ORCPT ); Thu, 26 Nov 2015 08:47:49 -0500 Received: from mailout3.samsung.com ([203.254.224.33]:57988 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751198AbbKZNrn (ORCPT ); Thu, 26 Nov 2015 08:47:43 -0500 Received: from epcpsbgr3.samsung.com (u143.gpu120.samsung.co.kr [203.254.230.143]) by mailout3.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0NYF01HZZCZH1U10@mailout3.samsung.com>; Thu, 26 Nov 2015 22:47:41 +0900 (KST) Received: from epcpsbgm2new.samsung.com ( [172.20.52.112]) by epcpsbgr3.samsung.com (EPCPMTA) with SMTP id B5.1A.30395.C7D07565; Thu, 26 Nov 2015 22:47:40 +0900 (KST) X-AuditID: cbfee68f-f79666d0000076bb-a7-56570d7ce0f3 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2new.samsung.com (EPCPMTA) with SMTP id 8D.9F.00996.C7D07565; Thu, 26 Nov 2015 22:47:40 +0900 (KST) Received: from chan.10.32.193.11 ([10.252.81.195]) by mmp1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0NYF00D4UCZGTXL0@mmp1.samsung.com>; Thu, 26 Nov 2015 22:47:40 +0900 (KST) From: Chanwoo Choi To: myungjoo.ham@samsung.com, kyungmin.park@samsung.com, kgene@kernel.org, k.kozlowski@samsung.com Cc: robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux@arm.linux.org.uk, tjakobi@math.uni-bielefeld.de, cw00.choi@samsung.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org Subject: [RFC PATCH 02/15] PM / devfreq: exynos: Add documentation for generic exynos bus frequency driver Date: Thu, 26 Nov 2015 22:47:26 +0900 Message-id: <1448545659-32287-3-git-send-email-cw00.choi@samsung.com> X-Mailer: git-send-email 1.8.0 In-reply-to: <1448545659-32287-1-git-send-email-cw00.choi@samsung.com> References: <1448545659-32287-1-git-send-email-cw00.choi@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprKIsWRmVeSWpSXmKPExsWyRsSkQLeGNzzM4Hu3tcX1L89ZLeYfOcdq 0f9mIavFuVcrGS1evzC06H/8mtnibNMbdovLu+awWXzuPcJoMeP8PiaL25d5LZZevwhkNK5g s5gwfS2LReveI+wWbas/sDoIeKyZt4bRo6W5h83jcl8vk8fK5V/YPDat6mTz+HeM3aNvyypG j8+b5AI4orhsUlJzMstSi/TtErgydqydw1LwQrbibMMUpgbGJokuRk4OCQETiUPd51kgbDGJ C/fWs3UxcnEICaxglOj9e5gdpujwhvtMEImljBIrzsNUfWGUuPl4AiNIFZuAlsT+FzfYQGwR gRSJvzdnM4IUMQscYpI48+4IE0hCWCBHYtGyKWA2i4CqxPJpr1i7GDk4eAVcJe70WkNsk5P4 sOcR2GZOATeJU1cmgc0XAiqZ/LEHbLGEwEd2iRu7VrNAzBGQ+Db5EAvIHAkBWYlNB5gh5khK HFxxg2UCo/ACRoZVjKKpBckFxUnpRcZ6xYm5xaV56XrJ+bmbGIGxdfrfs/4djHcPWB9iFOBg VOLhLbANCxNiTSwrrsw9xGgKtGEis5Rocj4wgvNK4g2NzYwsTE1MjY3MLc2UxHkXSv0MFhJI TyxJzU5NLUgtii8qzUktPsTIxMEp1cDoePZ/ld3S0MwJ265MDe60fNc5s6ZVZa/sudg3NXtb eJ243lt7Vgmcv9SVeij2x/W4akV+8WkSOkIztC13L2OYY57okD17784CL9fsXy2WGu5SVp/v 3LLe3+u1jNuzqym/sKVqufScG7lHnVxfz3xwubi44mW0MYNPVNdUY6HgzoIS6Tvr1ZVYijMS DbWYi4oTAaW4xpWoAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrEIsWRmVeSWpSXmKPExsVy+t9jAd0a3vAwg2//TCyuf3nOajH/yDlW i/43C1ktzr1ayWjx+oWhRf/j18wWZ5vesFtc3jWHzeJz7xFGixnn9zFZ3L7Ma7H0+kUgo3EF m8WE6WtZLFr3HmG3aFv9gdVBwGPNvDWMHi3NPWwel/t6mTxWLv/C5rFpVSebx79j7B59W1Yx enzeJBfAEdXAaJORmpiSWqSQmpecn5KZl26r5B0c7xxvamZgqGtoaWGupJCXmJtqq+TiE6Dr lpkD9ICSQlliTilQKCCxuFhJ3w7ThNAQN10LmMYIXd+QILgeIwM0kLCGMWPH2jksBS9kK842 TGFqYGyS6GLk5JAQMJE4vOE+E4QtJnHh3nq2LkYuDiGBpYwSK87DOF8YJW4+nsAIUsUmoCWx /8UNNhBbRCBF4u/N2YwgRcwCh5gkzrw7AjZKWCBHYtGyKWA2i4CqxPJpr1i7GDk4eAVcJe70 WkNsk5P4sOcRO4jNKeAmcerKJLD5QkAlkz/2sE1g5F3AyLCKUSK1ILmgOCk91ygvtVyvODG3 uDQvXS85P3cTIzh+n0nvYDy8y/0QowAHoxIPb4FtWJgQa2JZcWXuIUYJDmYlEd5bLOFhQrwp iZVVqUX58UWlOanFhxhNge6ayCwlmpwPTC15JfGGxiZmRpZG5oYWRsbmSuK8F/b7hQkJpCeW pGanphakFsH0MXFwSjUwHshSOm0XNnfvlKp6a5/nMy9WCbf9LF/18N6Zlb6vHLo5860v/mnf dPjx4ov68k2KZwV+W627kxBZvij2wUJbz8Vvvfe88xQXTV7147XyvuizJwN2uERGOC34Ee25 /Gxfn8Yn486edVtYt4kvSrgTZXLTS2XjW+6unC2XHS9uSHwxQ+ZC43UpLyWW4oxEQy3mouJE ALTm8Wv1AgAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the documentation for generic exynos bus frequency driver. Signed-off-by: Chanwoo Choi --- .../devicetree/bindings/devfreq/exynos-bus.txt | 92 ++++++++++++++++++++++ 1 file changed, 92 insertions(+) create mode 100644 Documentation/devicetree/bindings/devfreq/exynos-bus.txt diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt new file mode 100644 index 000000000000..5d90623bd173 --- /dev/null +++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt @@ -0,0 +1,92 @@ +* Generic Exynos Bus frequency device + +The Samsung Exynos SoC have many buses for data transfer between DRAM +and sub-blocks in SoC. Almost Exynos SoC have the common architecture +for buses. Generally, the each bus of Exynos SoC includes the source clock +and power line and then is able to change the clock according to the usage +of each buses on runtime. When gathering the usage of each buses on runtime, +thie driver uses the exynos-ppmu.c driver with DEVFREQ-EVENT framework. + +There are a little different composition among Exynos SoC because each Exynos +SoC has the different sub-blocks. So, this difference should be specified +in devicetree file instead of each device driver. In result, this driver +is able to support the bus frequency for all Exynos SoCs. + +Required properties for bus device: +- compatible: Should be "samsung,exynos-bus". +- clock-names : the name of clock used by the bus, "bus". +- clocks : phandles for clock specified in "clock-names" property. +- #clock-cells: should be 1. +- operating-points-v2: the OPP table including frequency/voltage information + to support DVFS (Dynamic Voltage/Frequency Scaling) feature. +- vdd-supply: the regulator to provide the buses with the voltage. +- devfreq-events: the devfreq-event device to monitor the curret utilization + of buses. + +Optional properties for bus device: +- exynos,saturation-ratio: the percentage value which is used to calibrate + the performance count againt total cycle count. + +Example1: + Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to + power line (regulator). The MIF (Memory Interface) AXI bus is used to + transfer data between DRAM and CPU and uses the VDD_MIF regualtor. + + - power line(VDD_MIF) --> bus for DMC block (dmc clock) + + - MIF bus's frequency/voltage table + ----------------------- + |Lv| Freq | Voltage | + ----------------------- + |L1| 50000 |800000 | + |L2| 100000 |800000 | + |L3| 133000 |800000 | + |L4| 200000 |800000 | + |L5| 400000 |875000 | + ----------------------- + +Example2 : + The bus of DMC block in exynos3250.dtsi are listed below: + + bus_dmc: bus_dmc { + compatible = "samsung,exynos-bus"; + clocks = <&cmu_dmc CLK_DIV_DMC>; + clock-names = "bus"; + operating-points-v2 = <&bus_dmc_opp_table>; + status = "disabled"; + }; + + bus_dmc_opp_table: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp00 { + opp-hz = /bits/ 64 <50000000>; + opp-microvolt = <800000>; + }; + opp01 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <800000>; + }; + opp02 { + opp-hz = /bits/ 64 <133000000>; + opp-microvolt = <800000>; + }; + opp03 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <800000>; + }; + opp04 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <875000>; + }; + }; + + Usage case to handle the frequency and voltage of bus on runtime + in exynos3250-rinato.dts are listed below: + + &bus_dmc { + devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; + vdd-supply = <&buck1_reg>; /* VDD_MIF */ + status = "okay"; + };