From patchwork Thu Dec 3 08:48:43 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Caesar Wang X-Patchwork-Id: 7757481 X-Patchwork-Delegate: eduardo.valentin@ti.com Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 7CED9BEEE1 for ; Thu, 3 Dec 2015 09:06:18 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 166A22051D for ; Thu, 3 Dec 2015 09:06:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 320E8204A9 for ; Thu, 3 Dec 2015 09:06:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932328AbbLCJGK (ORCPT ); Thu, 3 Dec 2015 04:06:10 -0500 Received: from mail-pa0-f66.google.com ([209.85.220.66]:34033 "EHLO mail-pa0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758865AbbLCJGG (ORCPT ); Thu, 3 Dec 2015 04:06:06 -0500 Received: by pacfl14 with SMTP id fl14so8187090pac.1; Thu, 03 Dec 2015 01:06:05 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=cQlMkzYoMYW+jkVr6MJgIOm6P7+CYIxGQzsI3JQiwOA=; b=lIHUVge1HGbzvKmA84Ofxq2OHtUVCwJHUowbMctWRAP+yjTHfwRsxffAihswvQE157 gGjH8bC2vyLKpojhUJfLPn2WrjC2TFd0pgs0tuwjc2dMXrJWeveK/gZKI3ywVKxmRQWX HHcmur+sXc6+cElUmom2M31GL1tuHcyym1dnlHCuYJ8xCccRf/m4yRXvPmDQygDprwRa 9yf9g9roUDSZo6dX2/NP3pjtDmFmqNfbfQHLnZlly4pkpBAo/qGKdEjXItbHhPNpONfv box/5tywVmHMkWvCu2bXg49xttvDeHnB+IhhBRJyRQs/KUyFBokaohsKF8Ws1kq4JmOD 8PIA== X-Received: by 10.66.117.199 with SMTP id kg7mr11401308pab.105.1449132567076; Thu, 03 Dec 2015 00:49:27 -0800 (PST) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id 13sm9087741pfp.68.2015.12.03.00.49.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 03 Dec 2015 00:49:26 -0800 (PST) From: Caesar Wang To: Eduardo Valentin Cc: huangtao@rock-chips.com, Heiko Stuebner , dmitry.torokhov@gmail.com, dianders@chromium.org, linux-rockchip@lists.infradead.org, computersforpeace@gmail.com, Dan Carpenter , Caesar Wang , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, Zhang Rui , linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 5/5] thermal: rockchip: Support the RK3399 SoCs in thermal driver Date: Thu, 3 Dec 2015 16:48:43 +0800 Message-Id: <1449132523-18817-6-git-send-email-wxt@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1449132523-18817-1-git-send-email-wxt@rock-chips.com> References: <1449132523-18817-1-git-send-email-wxt@rock-chips.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The RK3399 SoCs have two Temperature Sensors, channel 0 is for CPU. channel 1 is for GPU. Signed-off-by: Caesar Wang --- Changes in v3: None Changes in v2: None Changes in v1: - fix a irq ack is similar with RK3228 SoCs. drivers/thermal/rockchip_thermal.c | 66 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_thermal.c index 95415ac..c597784 100644 --- a/drivers/thermal/rockchip_thermal.c +++ b/drivers/thermal/rockchip_thermal.c @@ -292,6 +292,44 @@ static const struct tsadc_table v3_code_table[] = { {TSADCV3_DATA_MASK, 125000}, }; +static const struct tsadc_table v4_code_table[] = { + {TSADCV3_DATA_MASK, -40000}, + {431, -40000}, + {426, -35000}, + {421, -30000}, + {415, -25000}, + {410, -20000}, + {405, -15000}, + {399, -10000}, + {394, -5000}, + {389, 0}, + {383, 5000}, + {378, 10000}, + {373, 15000}, + {367, 20000}, + {362, 25000}, + {357, 30000}, + {351, 35000}, + {346, 40000}, + {340, 45000}, + {335, 50000}, + {330, 55000}, + {324, 60000}, + {319, 65000}, + {313, 70000}, + {308, 75000}, + {302, 80000}, + {297, 85000}, + {291, 90000}, + {286, 95000}, + {281, 100000}, + {275, 105000}, + {270, 110000}, + {264, 115000}, + {259, 120000}, + {253, 125000}, +}; + static u32 rk_tsadcv2_temp_to_code(struct chip_tsadc_table table, int temp) { @@ -555,6 +593,30 @@ static const struct rockchip_tsadc_chip rk3368_tsadc_data = { }, }; +static const struct rockchip_tsadc_chip rk3399_tsadc_data = { + .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ + .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ + .chn_num = 2, /* two channels for tsadc */ + + .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ + .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ + .tshut_temp = 95000, + + .initialize = rk_tsadcv2_initialize, + .irq_ack = rk_tsadcv1_irq_ack, + .control = rk_tsadcv2_control, + .get_temp = rk_tsadcv2_get_temp, + .set_tshut_temp = rk_tsadcv2_tshut_temp, + .set_tshut_mode = rk_tsadcv2_tshut_mode, + + .table = { + .id = v4_code_table, + .length = ARRAY_SIZE(v4_code_table), + .data_mask = TSADCV3_DATA_MASK, + .mode = ADC_DECREMENT, + }, +}; + static const struct of_device_id of_rockchip_thermal_match[] = { { .compatible = "rockchip,rk3228-tsadc", @@ -568,6 +630,10 @@ static const struct of_device_id of_rockchip_thermal_match[] = { .compatible = "rockchip,rk3368-tsadc", .data = (void *)&rk3368_tsadc_data, }, + { + .compatible = "rockchip,rk3399-tsadc", + .data = (void *)&rk3399_tsadc_data, + }, { /* end */ }, }; MODULE_DEVICE_TABLE(of, of_rockchip_thermal_match);