From patchwork Fri Dec 4 14:57:13 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 7768841 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 3CA5D9F30B for ; Fri, 4 Dec 2015 15:02:37 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3FC5A205E4 for ; Fri, 4 Dec 2015 15:02:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 51E6B205ED for ; Fri, 4 Dec 2015 15:02:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754568AbbLDPBE (ORCPT ); Fri, 4 Dec 2015 10:01:04 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:5603 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754390AbbLDPA7 (ORCPT ); Fri, 4 Dec 2015 10:00:59 -0500 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Fri, 04 Dec 2015 07:01:05 -0800 Received: from hqemhub03.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Fri, 04 Dec 2015 06:47:38 -0800 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Fri, 04 Dec 2015 06:47:38 -0800 Received: from jonathanh-lm.nvidia.com (172.20.144.16) by hqemhub03.nvidia.com (172.20.150.15) with Microsoft SMTP Server (TLS) id 8.3.406.0; Fri, 4 Dec 2015 07:00:58 -0800 From: Jon Hunter To: Philipp Zabel , Stephen Warren , Thierry Reding , Alexandre Courbot , Rafael Wysocki , Kevin Hilman , Ulf Hansson , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala CC: Vince Hsu , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, Jon Hunter Subject: [PATCH V4 12/16] Documentation: DT: bindings: Add power domain info for NVIDIA PMC Date: Fri, 4 Dec 2015 14:57:13 +0000 Message-ID: <1449241037-22193-13-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1449241037-22193-1-git-send-email-jonathanh@nvidia.com> References: <1449241037-22193-1-git-send-email-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add power-domain binding documentation for the NVIDIA PMC driver in order to support generic power-domains. Signed-off-by: Jon Hunter --- Please note that I have been debating whether I add this "nvidia,powergate-clock-disable" property or just leave the clocks disabled by default. Some downstream kernels leave the clocks enabled for the audio power-domain because the clocks required for powering up the power-domain are needed by all modules within the power-domain. However are the same time there are other power-domains that may need to be on, but not always clocked and so having the ability to specify if the clocks should be disabled seems useful. However, I can also remove this and just have the appropriate devices turn on the clocks as well. --- .../bindings/arm/tegra/nvidia,tegra20-pmc.txt | 61 ++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt index 838e1a69ec0a..8e4641db51a9 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.txt @@ -1,5 +1,7 @@ NVIDIA Tegra Power Management Controller (PMC) +== Power Management Controller Node == + The PMC block interacts with an external Power Management Unit. The PMC mostly controls the entry and exit of the system from different sleep modes. It provides power-gating controllers for SoC and CPU power-islands. @@ -69,6 +71,10 @@ Optional properties for hardware-triggered thermal reset (inside 'i2c-thermtrip' Defaults to 0. Valid values are described in section 12.5.2 "Pinmux Support" of the Tegra4 Technical Reference Manual. +Optional nodes: +- pm-domains : This node contains a hierarchy of PM domain nodes, which should + match the power-domains on the Tegra SoC. + Example: / SoC dts including file @@ -114,3 +120,58 @@ pmc@7000f400 { }; ... }; + + +== PM Domain Nodes == + +Each of the PM domain nodes represents a power-domain on the Tegra SoC +that can be power-gated by the PMC and should be named appropriately. + +Required properties: + - clocks: Must contain an entry for each clock required by the PMC for + controlling a power-gate. See ../clocks/clock-bindings.txt for details. + - resets: Must contain an entry for each reset required by the PMC for + controlling a power-gate. See ../reset/reset.txt for details. + - nvidia,powergate: Integer cell that contains an identifier for the PMC + power-gate that is associated with the power-domain. Please refer to + the Tegra TRM for more details. + - #power-domain-cells: Must be 0. + +Optional properties: + - nvidia,powergate-disable-clocks: Boolean property that if present + indicates that the clocks listed in the "clocks" property should be + disabled after turning on the power-domain. Otherwise the clocks will + be kept enabled. + +Example: + + pmc: pmc@0,7000e400 { + compatible = "nvidia,tegra210-pmc"; + reg = <0x0 0x7000e400 0x0 0x400>; + clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; + clock-names = "pclk", "clk32k_in"; + + pm-domains { + pd_audio: aud { + clocks = <&tegra_car TEGRA210_CLK_APE>, + <&tegra_car TEGRA210_CLK_APB2APE>; + resets = <&tegra_car 198>; + nvidia,powergate = ; + #power-domain-cells = <0>; + }; + }; + }; + + +== PM Domain Consumers == + +Hardware blocks belonging to a PM domain should contain a "power-domains" +property that is a phandle pointing to the corresponding PM domain node. + +Example: + + adma: adma@702e2000 { + ... + power-domains = <&pd_audio>; + ... + };