| Message ID | 1449585124-15596-5-git-send-email-lee.jones@linaro.org (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
On 08-12-15, 14:31, Lee Jones wrote: > diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi > index 81f8121..9fa1e58 100644 > --- a/arch/arm/boot/dts/stih407-family.dtsi > +++ b/arch/arm/boot/dts/stih407-family.dtsi > @@ -22,15 +22,29 @@ > device_type = "cpu"; > compatible = "arm,cortex-a9"; > reg = <0>; > + > /* u-boot puts hpen in SBC dmem at 0xa4 offset */ > cpu-release-addr = <0x94100A4>; > + > + /* kHz uV */ > + operating-points = <1500000 0 > + 1200000 0 > + 800000 0 > + 500000 0>; > }; > cpu@1 { > device_type = "cpu"; > compatible = "arm,cortex-a9"; > reg = <1>; > + > /* u-boot puts hpen in SBC dmem at 0xa4 offset */ > cpu-release-addr = <0x94100A4>; > + > + /* kHz uV */ > + operating-points = <1500000 0 > + 1200000 0 > + 800000 0 > + 500000 0>; Why didn't you move to opp-v2 ?
On Tue, 08 Dec 2015, Viresh Kumar wrote: > On 08-12-15, 14:31, Lee Jones wrote: > > diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi > > index 81f8121..9fa1e58 100644 > > --- a/arch/arm/boot/dts/stih407-family.dtsi > > +++ b/arch/arm/boot/dts/stih407-family.dtsi > > @@ -22,15 +22,29 @@ > > device_type = "cpu"; > > compatible = "arm,cortex-a9"; > > reg = <0>; > > + > > /* u-boot puts hpen in SBC dmem at 0xa4 offset */ > > cpu-release-addr = <0x94100A4>; > > + > > + /* kHz uV */ > > + operating-points = <1500000 0 > > + 1200000 0 > > + 800000 0 > > + 500000 0>; > > }; > > cpu@1 { > > device_type = "cpu"; > > compatible = "arm,cortex-a9"; > > reg = <1>; > > + > > /* u-boot puts hpen in SBC dmem at 0xa4 offset */ > > cpu-release-addr = <0x94100A4>; > > + > > + /* kHz uV */ > > + operating-points = <1500000 0 > > + 1200000 0 > > + 800000 0 > > + 500000 0>; > > Why didn't you move to opp-v2 ? Because we can't guarantee that the system was booted with a bootloader which supports opp-v2. This is the fall-back configuration. Please continue through the set.
diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi index 81f8121..9fa1e58 100644 --- a/arch/arm/boot/dts/stih407-family.dtsi +++ b/arch/arm/boot/dts/stih407-family.dtsi @@ -22,15 +22,29 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + /* u-boot puts hpen in SBC dmem at 0xa4 offset */ cpu-release-addr = <0x94100A4>; + + /* kHz uV */ + operating-points = <1500000 0 + 1200000 0 + 800000 0 + 500000 0>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + /* u-boot puts hpen in SBC dmem at 0xa4 offset */ cpu-release-addr = <0x94100A4>; + + /* kHz uV */ + operating-points = <1500000 0 + 1200000 0 + 800000 0 + 500000 0>; }; };
You'll notice that the voltage cell is populated with 0's. Voltage information is very platform specific, even depends on 'cut' and 'substrate' versions. Thus it is left blank for a generic (safe) implementation. If other nodes/properties are provided by the bootloader, the ST CPUFreq driver will over-ride these generic values. Signed-off-by: Lee Jones <lee.jones@linaro.org> --- arch/arm/boot/dts/stih407-family.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+)