From patchwork Fri Dec 11 22:40:36 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacob Pan X-Patchwork-Id: 7833121 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 1BD0E9F349 for ; Fri, 11 Dec 2015 22:42:35 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 3525920524 for ; Fri, 11 Dec 2015 22:42:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4350620495 for ; Fri, 11 Dec 2015 22:42:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754338AbbLKWmO (ORCPT ); Fri, 11 Dec 2015 17:42:14 -0500 Received: from mga14.intel.com ([192.55.52.115]:28346 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754230AbbLKWls (ORCPT ); Fri, 11 Dec 2015 17:41:48 -0500 Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga103.fm.intel.com with ESMTP; 11 Dec 2015 14:41:48 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.20,415,1444719600"; d="scan'208";a="839523424" Received: from icelake.jf.intel.com ([10.7.199.161]) by orsmga001.jf.intel.com with ESMTP; 11 Dec 2015 14:41:47 -0800 From: Jacob Pan To: LKML , Linux PM , Rafael Wysocki Cc: Peter Zijlstra , X86 Kernel , Srinivas Pandruvada , "H. Peter Anvin" , Thomas Gleixner , Ingo Molnar , Jacob Pan Subject: [PATCH 1/2] x86/msr: add on cpu read/modify/write function Date: Fri, 11 Dec 2015 14:40:36 -0800 Message-Id: <1449873637-24300-2-git-send-email-jacob.jun.pan@linux.intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1449873637-24300-1-git-send-email-jacob.jun.pan@linux.intel.com> References: <1449873637-24300-1-git-send-email-jacob.jun.pan@linux.intel.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Remote CPU read/modify/write is often needed but currently without a lib call. This patch adds an API to perform on CPU safe read/modify/write so that callers don't have to invent such function. Based on initial code from: Peter Zijlstra Suggested-by: Srinivas Pandruvada Signed-off-by: Jacob Pan --- arch/x86/include/asm/msr.h | 24 +++++++++++++++++++++++ arch/x86/lib/msr-smp.c | 47 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 71 insertions(+) diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index 77d8b28..6143a47 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -27,6 +27,13 @@ struct msr_info { int err; }; +struct msr_action { + u32 msr_no; + u64 mask; + u64 bits; + int err; +}; + struct msr_regs_info { u32 *regs; int err; @@ -258,6 +265,7 @@ int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); int wrmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q); int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); +int rmwmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 mask, u64 bits); #else /* CONFIG_SMP */ static inline int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h) { @@ -314,6 +322,22 @@ static inline int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) { return wrmsr_safe_regs(regs); } +static inline int rmwmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 mask, u64 bits) +{ + int err; + u64 val; + + err = rdmsrl_safe(msr_no, &val); + if (err) + goto out; + + val &= ~mask; + val |= bits; + + err = wrmsrl_safe(msr_no, val); +out: + return err; +} #endif /* CONFIG_SMP */ #endif /* __ASSEMBLY__ */ #endif /* _ASM_X86_MSR_H */ diff --git a/arch/x86/lib/msr-smp.c b/arch/x86/lib/msr-smp.c index 518532e..60ed278 100644 --- a/arch/x86/lib/msr-smp.c +++ b/arch/x86/lib/msr-smp.c @@ -221,6 +221,53 @@ int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) } EXPORT_SYMBOL(rdmsrl_safe_on_cpu); + +static void __rmwmsrl_safe(void *info) +{ + int err; + struct msr_action *ma = info; + u64 val; + + err = rdmsrl_safe(ma->msr_no, &val); + if (err) + goto out; + + val &= ~ma->mask; + val |= ma->bits; + + err = wrmsrl_safe(ma->msr_no, val); + +out: + ma->err = err; +} + +/** + * rmwmsrl_safe_on_cpu: Perform a read/modify/write msr transaction on cpu + * + * @cpu: target cpu + * @msr: msr number + * @mask: bitmask to change + * @bits: bits value for the mask + * + * Returns zero for success, a negative number on error. + */ +int rmwmsrl_safe_on_cpu(unsigned int cpu, u32 msr, u64 mask, u64 bits) +{ + int err; + struct msr_action ma; + + memset(&ma, 0, sizeof(ma)); + + ma.msr_no = msr; + ma.mask = mask; + ma.bits = bits; + + err = smp_call_function_single(cpu, __rmwmsrl_safe, &ma, 1); + + return err ? err : ma.err; +} +EXPORT_SYMBOL(rmwmsrl_safe_on_cpu); + /* * These variants are significantly slower, but allows control over * the entire 32-bit GPR set.