From patchwork Mon Feb 15 21:16:59 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 8319351 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id BCCE7C02AA for ; Mon, 15 Feb 2016 21:17:30 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DA080203B4 for ; Mon, 15 Feb 2016 21:17:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id EE3EA2041B for ; Mon, 15 Feb 2016 21:17:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752533AbcBOVRU (ORCPT ); Mon, 15 Feb 2016 16:17:20 -0500 Received: from baptiste.telenet-ops.be ([195.130.132.51]:59155 "EHLO baptiste.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752458AbcBOVRL (ORCPT ); Mon, 15 Feb 2016 16:17:11 -0500 Received: from ayla.of.borg ([84.195.106.123]) by baptiste.telenet-ops.be with bizsmtp id JlH81s00i2fm56U01lH8wi; Mon, 15 Feb 2016 22:17:10 +0100 Received: from ramsan.of.borg ([192.168.97.29] helo=ramsan) by ayla.of.borg with esmtp (Exim 4.82) (envelope-from ) id 1aVQW4-00082x-JL; Mon, 15 Feb 2016 22:17:08 +0100 Received: from geert by ramsan with local (Exim 4.82) (envelope-from ) id 1aVQW5-0004xg-AF; Mon, 15 Feb 2016 22:17:09 +0100 From: Geert Uytterhoeven To: Simon Horman , Magnus Damm , Laurent Pinchart Cc: linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH/RFC v2 10/11] ARM: dts: r8a7794: Add SYSC PM domains Date: Mon, 15 Feb 2016 22:16:59 +0100 Message-Id: <1455571020-18968-11-git-send-email-geert+renesas@glider.be> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1455571020-18968-1-git-send-email-geert+renesas@glider.be> References: <1455571020-18968-1-git-send-email-geert+renesas@glider.be> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add a device node for the System Controller, with subnodes that represent the hardware power area hierarchy. Hook up the Cortex-A7 CPU cores and the Cortex-A7 L2 cache/SCU to their respective PM domains. Signed-off-by: Geert Uytterhoeven --- v2: - Change one-line summary prefix to match current arm-soc practices, - Update compatible values. --- arch/arm/boot/dts/r8a7794.dtsi | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 21a02df3609b24aa..d0fc735571242fd1 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -40,6 +40,7 @@ compatible = "arm,cortex-a7"; reg = <0>; clock-frequency = <1000000000>; + power-domains = <&pd_ca7_cpu0>; next-level-cache = <&L2_CA7>; }; @@ -48,12 +49,14 @@ compatible = "arm,cortex-a7"; reg = <1>; clock-frequency = <1000000000>; + power-domains = <&pd_ca7_cpu1>; next-level-cache = <&L2_CA7>; }; }; L2_CA7: cache-controller@1 { compatible = "cache"; + power-domains = <&pd_ca7_scu>; cache-unified; cache-level = <2>; }; @@ -1152,6 +1155,43 @@ }; }; + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7794-sysc", "renesas,rcar-gen2-sysc"; + reg = <0 0xe6180000 0 0x0200>; + + pm-domains { + #address-cells = <2>; + #size-cells = <0>; + + pd_ca7_scu: scu@21 { + reg = <21 0x100>; + #address-cells = <2>; + #size-cells = <0>; + #power-domain-cells = <0>; + + pd_ca7_cpu0: cpu@5 { + reg = <5 0x1c0>; + #power-domain-cells = <0>; + }; + + pd_ca7_cpu1: cpu@6 { + reg = <6 0x1c0>; + #power-domain-cells = <0>; + }; + }; + + pd_sh: sh@16 { + reg = <16 0x80>; + #power-domain-cells = <0>; + }; + + pd_sgx: sgx@20 { + reg = <20 0xc0>; + #power-domain-cells = <0>; + }; + }; + }; + ipmmu_sy0: mmu@e6280000 { compatible = "renesas,ipmmu-r8a7794", "renesas,ipmmu-vmsa"; reg = <0 0xe6280000 0 0x1000>;