From patchwork Thu Feb 18 05:13:01 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 8345641 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 686C19F399 for ; Thu, 18 Feb 2016 05:14:23 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7C15220357 for ; Thu, 18 Feb 2016 05:14:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 817DF20384 for ; Thu, 18 Feb 2016 05:14:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752067AbcBRFNX (ORCPT ); Thu, 18 Feb 2016 00:13:23 -0500 Received: from mailout3.w1.samsung.com ([210.118.77.13]:24235 "EHLO mailout3.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750984AbcBRFNV (ORCPT ); Thu, 18 Feb 2016 00:13:21 -0500 Received: from eucpsbgm1.samsung.com (unknown [203.254.199.244]) by mailout3.w1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0O2Q0092P966V690@mailout3.w1.samsung.com>; Thu, 18 Feb 2016 05:13:18 +0000 (GMT) X-AuditID: cbfec7f4-f79026d00000418a-fc-56c552ed75a4 Received: from eusync4.samsung.com ( [203.254.199.214]) by eucpsbgm1.samsung.com (EUCPMTA) with SMTP id D1.FB.16778.DE255C65; Thu, 18 Feb 2016 05:13:17 +0000 (GMT) Received: from localhost.localdomain ([10.113.63.52]) by eusync4.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0O2Q002O995X2A80@eusync4.samsung.com>; Thu, 18 Feb 2016 05:13:17 +0000 (GMT) From: Krzysztof Kozlowski To: Kukjin Kim , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Cc: Lukasz Majewski , Zhang Rui , Eduardo Valentin , Viresh Kumar Subject: [PATCH v2 1/3] ARM: dts: Add cooling levels for CPUs on exynos5420 Date: Thu, 18 Feb 2016 14:13:01 +0900 Message-id: <1455772383-20598-1-git-send-email-k.kozlowski@samsung.com> X-Mailer: git-send-email 2.5.0 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprBLMWRmVeSWpSXmKPExsVy+t/xa7pvg46GGez+b20x/8g5Vov5V66x Wrx+YWjR//g1s8Wbh5sZLTY9Bgpd3jWHzeJz7xFGixnn9zFZPHnYx2ax8auHA7fHzll32T0W 73nJ5LFpVSebx51re9g8Ni+p9+jbsorR4/MmuQD2KC6blNSczLLUIn27BK6Mpc+XMRUsFK94 e+sHWwPjBKEuRk4OCQETiVXnVzFC2GISF+6tZ+ti5OIQEljKKPF44ioo5z+jxOefW9hAqtgE jCU2L18ClhAR+MwocfHrFBYQh1lgPqPEhCeLwWYJC3hLfJp7hRnEZhFQlZg68T87iM0r4C6x b+UZoDgH0D45iQUX0icwci9gZFjFKJpamlxQnJSea6hXnJhbXJqXrpecn7uJERJeX3YwLj5m dYhRgINRiYeX4/WRMCHWxLLiytxDjBIczEoivN/cj4YJ8aYkVlalFuXHF5XmpBYfYpTmYFES 5527632IkEB6YklqdmpqQWoRTJaJg1OqgZFb1cM/oCrgbeeG83uq9st/XXmUq0Z69u5p7BtY fe7N/5/JYaqzY3KyUO3GqQxfKwXqYv2swkX5vszO5zJPS+P5c262+/5kjW18z6IUb6h9U6mu nSf3XjYjLGOunnfLeess8aN1KUcWuvC+e3t86Rvbtg3fA45NDdScuOOczpyecI5lrt3qL5RY ijMSDbWYi4oTAQaD5bcrAgAA Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Exynos5420 we support 8 cpufreq steps (600-1300 MHz) for LITTLE and 12 steps for big core (700-1800 MHz). Add respective cooling cells. Signed-off-by: Krzysztof Kozlowski Acked-by: Viresh Kumar --- Changes since v1: 1. Add cooling properties to all CPUs (suggested by Viresh). --- arch/arm/boot/dts/exynos5420-cpus.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/exynos5420-cpus.dtsi b/arch/arm/boot/dts/exynos5420-cpus.dtsi index 261d25173f61..5c052d7ff554 100644 --- a/arch/arm/boot/dts/exynos5420-cpus.dtsi +++ b/arch/arm/boot/dts/exynos5420-cpus.dtsi @@ -33,6 +33,9 @@ clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; + cooling-min-level = <0>; + cooling-max-level = <11>; + #cooling-cells = <2>; /* min followed by max */ }; cpu1: cpu@1 { @@ -42,6 +45,9 @@ clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; + cooling-min-level = <0>; + cooling-max-level = <11>; + #cooling-cells = <2>; /* min followed by max */ }; cpu2: cpu@2 { @@ -51,6 +57,9 @@ clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; + cooling-min-level = <0>; + cooling-max-level = <11>; + #cooling-cells = <2>; /* min followed by max */ }; cpu3: cpu@3 { @@ -60,6 +69,9 @@ clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; + cooling-min-level = <0>; + cooling-max-level = <11>; + #cooling-cells = <2>; /* min followed by max */ }; cpu4: cpu@100 { @@ -70,6 +82,9 @@ clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; + cooling-min-level = <0>; + cooling-max-level = <7>; + #cooling-cells = <2>; /* min followed by max */ }; cpu5: cpu@101 { @@ -79,6 +94,9 @@ clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; + cooling-min-level = <0>; + cooling-max-level = <7>; + #cooling-cells = <2>; /* min followed by max */ }; cpu6: cpu@102 { @@ -88,6 +106,9 @@ clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; + cooling-min-level = <0>; + cooling-max-level = <7>; + #cooling-cells = <2>; /* min followed by max */ }; cpu7: cpu@103 { @@ -97,6 +118,9 @@ clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; + cooling-min-level = <0>; + cooling-max-level = <7>; + #cooling-cells = <2>; /* min followed by max */ }; }; };