From patchwork Thu Feb 18 05:13:02 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 8345671 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 2396AC0555 for ; Thu, 18 Feb 2016 05:14:26 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 431B720357 for ; Thu, 18 Feb 2016 05:14:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 43FA120384 for ; Thu, 18 Feb 2016 05:14:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S964784AbcBRFNj (ORCPT ); Thu, 18 Feb 2016 00:13:39 -0500 Received: from mailout4.w1.samsung.com ([210.118.77.14]:8215 "EHLO mailout4.w1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752624AbcBRFNY (ORCPT ); Thu, 18 Feb 2016 00:13:24 -0500 Received: from eucpsbgm2.samsung.com (unknown [203.254.199.245]) by mailout4.w1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0O2Q00MUC969I580@mailout4.w1.samsung.com>; Thu, 18 Feb 2016 05:13:21 +0000 (GMT) X-AuditID: cbfec7f5-f79b16d000005389-40-56c552f1b80a Received: from eusync4.samsung.com ( [203.254.199.214]) by eucpsbgm2.samsung.com (EUCPMTA) with SMTP id FD.50.21385.1F255C65; Thu, 18 Feb 2016 05:13:21 +0000 (GMT) Received: from localhost.localdomain ([10.113.63.52]) by eusync4.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0O2Q002O995X2A80@eusync4.samsung.com>; Thu, 18 Feb 2016 05:13:21 +0000 (GMT) From: Krzysztof Kozlowski To: Kukjin Kim , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Cc: Lukasz Majewski , Zhang Rui , Eduardo Valentin , Viresh Kumar Subject: [PATCH v2 2/3] ARM: dts: Add cooling levels for CPUs on exynos5422/5800 Date: Thu, 18 Feb 2016 14:13:02 +0900 Message-id: <1455772383-20598-2-git-send-email-k.kozlowski@samsung.com> X-Mailer: git-send-email 2.5.0 In-reply-to: <1455772383-20598-1-git-send-email-k.kozlowski@samsung.com> References: <1455772383-20598-1-git-send-email-k.kozlowski@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrPLMWRmVeSWpSXmKPExsVy+t/xa7ofg46GGTTsZLGYf+Qcq8X8K9dY LV6/MLTof/ya2eLNw82MFpseA4Uu75rDZvG59wijxYzz+5gsnjzsY7PY+NXDgdtj56y77B6L 97xk8ti0qpPN4861PWwem5fUe/RtWcXo8XmTXAB7FJdNSmpOZllqkb5dAldG55eFjAWbxSs+ LGxga2BcINTFyMkhIWAisfDVXSYIW0ziwr31bF2MXBxCAksZJbYe2Qvl/GeU+PljMgtIFZuA scTm5UvAEiICnxklLn6dwgLiMAvMZ5SY8GQxI0iVsECAxLRte1m7GDk4WARUJdrWgK3gFXCX mHqqDSwsISAnseBCOkiYU8BDYvKP/8wgthBQyasVL9kmMPIuYGRYxSiaWppcUJyUnmukV5yY W1yal66XnJ+7iRESjF93MC49ZnWIUYCDUYmHd8OLI2FCrIllxZW5hxglOJiVRHi/uR8NE+JN SaysSi3Kjy8qzUktPsQozcGiJM47c9f7ECGB9MSS1OzU1ILUIpgsEwenVAPjGpFNFtPmXPVJ OLHB2Jj3uqNbuuXvz6/Tji2af/9e+8tbQUaV1nY5CrMXGAr+3X/rDvNHzWcC1wTaXv2ZcJNz u739jb/3MpWOi/VoaefUCclPOciVvVvw558HDfFG2/39fv/9uod37hLPqpm+Qf33X84KfTQ7 oXPtri559Xru9b1BRxSyS1abKrEUZyQaajEXFScCAOAER0VCAgAA Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Exynos5422 and Exynos5800 we support 12 cpufreq steps (200-1300 MHz) for LITTLE and 18 steps for big core (200-1700 MHz). Add respective cooling cells. Signed-off-by: Krzysztof Kozlowski Acked-by: Viresh Kumar --- Changes since v1: 1. Add cooling properties to all CPUs (suggested by Viresh). --- arch/arm/boot/dts/exynos5422-cpus.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi index 9b46b9fbac4e..bf3c6f1ec4ee 100644 --- a/arch/arm/boot/dts/exynos5422-cpus.dtsi +++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi @@ -32,6 +32,9 @@ clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; + cooling-min-level = <0>; + cooling-max-level = <11>; + #cooling-cells = <2>; /* min followed by max */ }; cpu1: cpu@101 { @@ -41,6 +44,9 @@ clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; + cooling-min-level = <0>; + cooling-max-level = <11>; + #cooling-cells = <2>; /* min followed by max */ }; cpu2: cpu@102 { @@ -50,6 +56,9 @@ clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; + cooling-min-level = <0>; + cooling-max-level = <11>; + #cooling-cells = <2>; /* min followed by max */ }; cpu3: cpu@103 { @@ -59,6 +68,9 @@ clock-frequency = <1000000000>; cci-control-port = <&cci_control0>; operating-points-v2 = <&cluster_a7_opp_table>; + cooling-min-level = <0>; + cooling-max-level = <11>; + #cooling-cells = <2>; /* min followed by max */ }; cpu4: cpu@0 { @@ -69,6 +81,9 @@ clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; + cooling-min-level = <0>; + cooling-max-level = <15>; + #cooling-cells = <2>; /* min followed by max */ }; cpu5: cpu@1 { @@ -78,6 +93,9 @@ clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; + cooling-min-level = <0>; + cooling-max-level = <15>; + #cooling-cells = <2>; /* min followed by max */ }; cpu6: cpu@2 { @@ -87,6 +105,9 @@ clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; + cooling-min-level = <0>; + cooling-max-level = <15>; + #cooling-cells = <2>; /* min followed by max */ }; cpu7: cpu@3 { @@ -96,6 +117,9 @@ clock-frequency = <1800000000>; cci-control-port = <&cci_control1>; operating-points-v2 = <&cluster_a15_opp_table>; + cooling-min-level = <0>; + cooling-max-level = <15>; + #cooling-cells = <2>; /* min followed by max */ }; }; };