From patchwork Fri Mar 11 03:09:14 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Wei Ni X-Patchwork-Id: 8561671 X-Patchwork-Delegate: eduardo.valentin@ti.com Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id AB89D9FDE7 for ; Fri, 11 Mar 2016 03:12:42 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id B6BD82035D for ; Fri, 11 Mar 2016 03:12:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id BA50B20108 for ; Fri, 11 Mar 2016 03:12:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933456AbcCKDJr (ORCPT ); Thu, 10 Mar 2016 22:09:47 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:3127 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933600AbcCKDJo (ORCPT ); Thu, 10 Mar 2016 22:09:44 -0500 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Thu, 10 Mar 2016 19:10:09 -0800 Received: from HQMAIL105.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Thu, 10 Mar 2016 19:09:05 -0800 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Thu, 10 Mar 2016 19:09:05 -0800 Received: from HKMAIL101.nvidia.com (10.18.16.10) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Fri, 11 Mar 2016 03:09:42 +0000 Received: from niwei-dev.nvidia.com (10.19.224.146) by HKMAIL101.nvidia.com (10.18.16.10) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Fri, 11 Mar 2016 03:09:39 +0000 From: Wei Ni To: , , CC: , , , , , , Wei Ni Subject: [PATCH V7 03/12] thermal: tegra: get rid of PDIV/HOTSPOT hack Date: Fri, 11 Mar 2016 11:09:14 +0800 Message-ID: <1457665763-29781-4-git-send-email-wni@nvidia.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1457665763-29781-1-git-send-email-wni@nvidia.com> References: <1457665763-29781-1-git-send-email-wni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 X-Originating-IP: [10.19.224.146] X-ClientProxiedBy: DRBGMAIL102.nvidia.com (10.18.16.21) To HKMAIL101.nvidia.com (10.18.16.10) Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Get rid of T124-specific PDIV/HOTSPOT hack. tegra-soctherm.c contained a hack to set the SENSOR_PDIV and SENSOR_HOTSPOT_OFFSET registers - it just did two writes of T124-specific opaque values. Convert these into a form that can be substituted on a per-chip basis, and into structure fields that have at least some independent meaning. Signed-off-by: Wei Ni --- drivers/thermal/tegra/tegra-soctherm.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/thermal/tegra/tegra-soctherm.c b/drivers/thermal/tegra/tegra-soctherm.c index b3ec0faa2bee..b4b791ebfbb6 100644 --- a/drivers/thermal/tegra/tegra-soctherm.c +++ b/drivers/thermal/tegra/tegra-soctherm.c @@ -48,14 +48,12 @@ #define SENSOR_CONFIG2_THERMB_SHIFT 0 #define SENSOR_PDIV 0x1c0 -#define SENSOR_PDIV_T124 0x8888 #define SENSOR_PDIV_CPU_MASK (0xf << 12) #define SENSOR_PDIV_GPU_MASK (0xf << 8) #define SENSOR_PDIV_MEM_MASK (0xf << 4) #define SENSOR_PDIV_PLLX_MASK (0xf << 0) #define SENSOR_HOTSPOT_OFF 0x1c4 -#define SENSOR_HOTSPOT_OFF_T124 0x00060600 #define SENSOR_HOTSPOT_CPU_MASK (0xff << 16) #define SENSOR_HOTSPOT_GPU_MASK (0xff << 8) #define SENSOR_HOTSPOT_MEM_MASK (0xff << 0) @@ -436,6 +434,7 @@ static int tegra_soctherm_probe(struct platform_device *pdev) struct resource *res; unsigned int i; int err; + u32 pdiv, hotspot; const struct tegra_tsensor *tsensors = t124_tsensors; const struct tegra_tsensor_group **ttgs = tegra124_tsensor_groups; @@ -493,8 +492,19 @@ static int tegra_soctherm_probe(struct platform_device *pdev) goto disable_clocks; } - writel(SENSOR_PDIV_T124, tegra->regs + SENSOR_PDIV); - writel(SENSOR_HOTSPOT_OFF_T124, tegra->regs + SENSOR_HOTSPOT_OFF); + /* Program pdiv and hotspot offsets per THERM */ + pdiv = readl(tegra->regs + SENSOR_PDIV); + hotspot = readl(tegra->regs + SENSOR_HOTSPOT_OFF); + for (i = 0; i < TEGRA124_SOCTHERM_SENSOR_NUM; ++i) { + pdiv = REG_SET_MASK(pdiv, ttgs[i]->pdiv_mask, + ttgs[i]->pdiv); + if (ttgs[i]->id != TEGRA124_SOCTHERM_SENSOR_PLLX) + hotspot = REG_SET_MASK(hotspot, + ttgs[i]->pllx_hotspot_mask, + ttgs[i]->pllx_hotspot_diff); + } + writel(pdiv, tegra->regs + SENSOR_PDIV); + writel(hotspot, tegra->regs + SENSOR_HOTSPOT_OFF); /* Initialize thermctl sensors */