From patchwork Fri Apr 22 09:07:26 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Geert Uytterhoeven X-Patchwork-Id: 8907261 Return-Path: X-Original-To: patchwork-linux-pm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 99C859F1C1 for ; Fri, 22 Apr 2016 09:07:50 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id A92D8201F5 for ; Fri, 22 Apr 2016 09:07:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id ACBF92025A for ; Fri, 22 Apr 2016 09:07:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754106AbcDVJHp (ORCPT ); Fri, 22 Apr 2016 05:07:45 -0400 Received: from laurent.telenet-ops.be ([195.130.137.89]:59448 "EHLO laurent.telenet-ops.be" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754105AbcDVJHj (ORCPT ); Fri, 22 Apr 2016 05:07:39 -0400 Received: from ayla.of.borg ([84.195.109.243]) by laurent.telenet-ops.be with bizsmtp id lM7d1s00K5F7gFG01M7d56; Fri, 22 Apr 2016 11:07:37 +0200 Received: from ramsan.of.borg ([192.168.97.29] helo=ramsan) by ayla.of.borg with esmtp (Exim 4.82) (envelope-from ) id 1atX3p-0006xP-Gw; Fri, 22 Apr 2016 11:07:37 +0200 Received: from geert by ramsan with local (Exim 4.82) (envelope-from ) id 1atX3p-0007Ih-LY; Fri, 22 Apr 2016 11:07:37 +0200 From: Geert Uytterhoeven To: Simon Horman , Magnus Damm Cc: Laurent Pinchart , linux-renesas-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, Geert Uytterhoeven Subject: [PATCH v6 04/12] ARM: dts: r8a7790: Add SYSC PM Domains Date: Fri, 22 Apr 2016 11:07:26 +0200 Message-Id: <1461316054-27999-5-git-send-email-geert+renesas@glider.be> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1461316054-27999-1-git-send-email-geert+renesas@glider.be> References: <1461316054-27999-1-git-send-email-geert+renesas@glider.be> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Spam-Status: No, score=-7.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add a device node for the System Controller. Hook up the Cortex-A15 and Cortex-A7 CPU cores and L2 caches/SCUs to their respective PM Domains. Signed-off-by: Geert Uytterhoeven Acked-by: Laurent Pinchart --- v6: - Add Acked-by, v5: - Remove "power-domains" property again from the sysc node, as the System Controller itself is not part of the Clock Domain, v4: - Add "power-domains" property to the sysc node, to refer to the SoC's Clock Domain, v3: - Drop power area hiearchy from DT, - Switch to "#power-domain-cells = <1>", - Drop fallback compatibility strings, v2: - Change one-line summary prefix to match current arm-soc practices, - Update compatible values. --- arch/arm/boot/dts/r8a7790.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 776a2aed81d2eff1..36c91d921771336a 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -13,6 +13,7 @@ #include #include #include +#include / { compatible = "renesas,r8a7790"; @@ -52,6 +53,7 @@ voltage-tolerance = <1>; /* 1% */ clocks = <&cpg_clocks R8A7790_CLK_Z>; clock-latency = <300000>; /* 300 us */ + power-domains = <&sysc R8A7790_PD_CA15_CPU0>; next-level-cache = <&L2_CA15>; /* kHz - uV - OPPs unknown yet */ @@ -68,6 +70,7 @@ compatible = "arm,cortex-a15"; reg = <1>; clock-frequency = <1300000000>; + power-domains = <&sysc R8A7790_PD_CA15_CPU1>; next-level-cache = <&L2_CA15>; }; @@ -76,6 +79,7 @@ compatible = "arm,cortex-a15"; reg = <2>; clock-frequency = <1300000000>; + power-domains = <&sysc R8A7790_PD_CA15_CPU2>; next-level-cache = <&L2_CA15>; }; @@ -84,6 +88,7 @@ compatible = "arm,cortex-a15"; reg = <3>; clock-frequency = <1300000000>; + power-domains = <&sysc R8A7790_PD_CA15_CPU3>; next-level-cache = <&L2_CA15>; }; @@ -92,6 +97,7 @@ compatible = "arm,cortex-a7"; reg = <0x100>; clock-frequency = <780000000>; + power-domains = <&sysc R8A7790_PD_CA7_CPU0>; next-level-cache = <&L2_CA7>; }; @@ -100,6 +106,7 @@ compatible = "arm,cortex-a7"; reg = <0x101>; clock-frequency = <780000000>; + power-domains = <&sysc R8A7790_PD_CA7_CPU1>; next-level-cache = <&L2_CA7>; }; @@ -108,6 +115,7 @@ compatible = "arm,cortex-a7"; reg = <0x102>; clock-frequency = <780000000>; + power-domains = <&sysc R8A7790_PD_CA7_CPU2>; next-level-cache = <&L2_CA7>; }; @@ -116,6 +124,7 @@ compatible = "arm,cortex-a7"; reg = <0x103>; clock-frequency = <780000000>; + power-domains = <&sysc R8A7790_PD_CA7_CPU3>; next-level-cache = <&L2_CA7>; }; }; @@ -141,12 +150,14 @@ L2_CA15: cache-controller@0 { compatible = "cache"; + power-domains = <&sysc R8A7790_PD_CA15_SCU>; cache-unified; cache-level = <2>; }; L2_CA7: cache-controller@1 { compatible = "cache"; + power-domains = <&sysc R8A7790_PD_CA7_SCU>; cache-unified; cache-level = <2>; }; @@ -1450,6 +1461,12 @@ }; }; + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7790-sysc"; + reg = <0 0xe6180000 0 0x0200>; + #power-domain-cells = <1>; + }; + qspi: spi@e6b10000 { compatible = "renesas,qspi-r8a7790", "renesas,qspi"; reg = <0 0xe6b10000 0 0x2c>;