From patchwork Thu Jun 9 00:43:35 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Derek Basehore X-Patchwork-Id: 9166059 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 651AA60467 for ; Thu, 9 Jun 2016 00:44:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 55BE8281F9 for ; Thu, 9 Jun 2016 00:44:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4A69628309; Thu, 9 Jun 2016 00:44:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D8A352823D for ; Thu, 9 Jun 2016 00:44:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1424554AbcFIAoi (ORCPT ); Wed, 8 Jun 2016 20:44:38 -0400 Received: from mail-pa0-f54.google.com ([209.85.220.54]:36250 "EHLO mail-pa0-f54.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1422885AbcFIAns (ORCPT ); Wed, 8 Jun 2016 20:43:48 -0400 Received: by mail-pa0-f54.google.com with SMTP id b5so7203149pas.3 for ; Wed, 08 Jun 2016 17:43:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hSINYrVEMBMEwJ2eRDbKBgunzARwDTEUusWatw9Z7LA=; b=UDPwV1kgIF/GJqPNA3Ln2rYUAw5uWgR+aOmS7rzF3NoviQvUStLdHhysRf8R2/JPel EQVMmmM+sYPMtld0h0kdl7MIhRqkdkxEAy9FangdZnv1yXaa+sm54MlRBy+mw1vIUJm4 GeGPPDu7RC5zOaprEQuKIOl0D8qv07Mc8zItQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hSINYrVEMBMEwJ2eRDbKBgunzARwDTEUusWatw9Z7LA=; b=DAMH2HIqZXFrflbM9teQ2CEUEjFO4wsKds5pDEZ7daTyR8JSIRTHTwIi5Tb3JZkhs9 2pfV+5LGKWvBygrdcdiXJ5/7AJeU8CtZOjZNfIeK+Dse7kOn7dyj/UlYt0bkW2IVO0dH 6H8Xi/fFrnnPr8ydQLH+veIh3BJ87Nn9Ws0i3nYgKorMrqfwBEglJEMU6m8bTIQldgyc r1O0doDVuTUH7dPmHb6lwj/M2/DB5C3EsUi1nJG2z6ZA/KF+cwgZfH/FRFE22ISCEmIX BKVZOBSnGoNpwNONieM5rPQaENiOXTKH4Des9yfhXtsRqtImB9O+83AwcnSJKfMRLEEl hk3A== X-Gm-Message-State: ALyK8tLuqPJ3G6S5uVjkzRQFcKqmBiUQMayUznqRAcBGMc7QZRbhepelXH38b/t4hCGYKVDK X-Received: by 10.66.34.68 with SMTP id x4mr8800481pai.1.1465433026893; Wed, 08 Jun 2016 17:43:46 -0700 (PDT) Received: from ketosis.mtv.corp.google.com ([172.22.65.104]) by smtp.gmail.com with ESMTPSA id cc6sm5094696pac.5.2016.06.08.17.43.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 08 Jun 2016 17:43:46 -0700 (PDT) From: dbasehore@chromium.org To: linux-kernel@vger.kernel.org Cc: dbasehore@chromium.org, linux-pm@vger.kernel.org, rjw@rjwysocki.net, pavel@ucw.cz, len.brown@intel.com, tglx@linutronix.de, gnomes@lxorguk.ukuu.org.uk, peterz@infradead.org Subject: [PATCH v2 3/5] x86, apic: Add timed freeze support Date: Wed, 8 Jun 2016 17:43:35 -0700 Message-Id: <1465433017-13602-4-git-send-email-dbasehore@chromium.org> X-Mailer: git-send-email 2.8.0.rc3.226.g39d4020 In-Reply-To: <1465433017-13602-1-git-send-email-dbasehore@chromium.org> References: <1465433017-13602-1-git-send-email-dbasehore@chromium.org> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Derek Basehore This adds support to the clock event devices created by apic to use timed freeze. The apic is able to run a timer during freeze with near izero impact on modern CPUs such as skylake. This will allow S0ix, suspend-to-idle, to be validated on Intel CPUs that support it. This is needed because bugs with power settings on the SoC can prevent S0ix entry. There is also no way to check this before idling all of the CPUs. Signed-off-by: Derek Basehore --- arch/x86/kernel/apic/apic.c | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 60078a6..f0c5f92 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -475,6 +475,26 @@ static int lapic_next_deadline(unsigned long delta, return 0; } +static bool lapic_event_expired(struct clock_event_device *evt) +{ + u32 cct; + + cct = apic_read(APIC_TMCCT); + return cct == 0; +} + +static bool lapic_deadline_expired(struct clock_event_device *evt) +{ + u64 msr; + + /* + * When the timer interrupt is triggered, the register is cleared, so a + * non-zero value indicates a pending timer event. + */ + rdmsrl(MSR_IA32_TSC_DEADLINE, msr); + return msr == 0; +} + static int lapic_timer_shutdown(struct clock_event_device *evt) { unsigned int v; @@ -529,12 +549,14 @@ static struct clock_event_device lapic_clockevent = { .name = "lapic", .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP - | CLOCK_EVT_FEAT_DUMMY, + | CLOCK_EVT_FEAT_DUMMY | + CLOCK_EVT_FEAT_FREEZE, .shift = 32, .set_state_shutdown = lapic_timer_shutdown, .set_state_periodic = lapic_timer_set_periodic, .set_state_oneshot = lapic_timer_set_oneshot, .set_next_event = lapic_next_event, + .event_expired = lapic_event_expired, .broadcast = lapic_timer_broadcast, .rating = 100, .irq = -1, @@ -562,6 +584,7 @@ static void setup_APIC_timer(void) levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_DUMMY); levt->set_next_event = lapic_next_deadline; + levt->event_expired = lapic_deadline_expired; clockevents_config_and_register(levt, (tsc_khz / TSC_DIVISOR) * 1000, 0xF, ~0UL);