From patchwork Thu Jun 9 21:02:17 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Derek Basehore X-Patchwork-Id: 9167905 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 46B5F60467 for ; Thu, 9 Jun 2016 21:02:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3A09528342 for ; Thu, 9 Jun 2016 21:02:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2ECF228347; Thu, 9 Jun 2016 21:02:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5D8DC28347 for ; Thu, 9 Jun 2016 21:02:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752121AbcFIVCf (ORCPT ); Thu, 9 Jun 2016 17:02:35 -0400 Received: from mail-pf0-f175.google.com ([209.85.192.175]:35890 "EHLO mail-pf0-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751948AbcFIVC2 (ORCPT ); Thu, 9 Jun 2016 17:02:28 -0400 Received: by mail-pf0-f175.google.com with SMTP id t190so16329688pfb.3 for ; Thu, 09 Jun 2016 14:02:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hSINYrVEMBMEwJ2eRDbKBgunzARwDTEUusWatw9Z7LA=; b=euLlqmrnN7vZyVeHXDW2rBx6m3gNBZsMzhdooEMq6FjTC8+KumKPtLT+8auaJ0oInn 1NeX1X8SekbV4L6WueTmtCw1ZLSd1YDe+0NODlDv1HKkif4oy5TsOt+Z3vgwyTgVywK0 XkFogSftQbapedWs2Pz9NAITAkIJRd+YCRsDc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hSINYrVEMBMEwJ2eRDbKBgunzARwDTEUusWatw9Z7LA=; b=C8SoTcE9wtNcQ2fUbz4iOJccgK3RLORk6Wdq+xo1yQdwkgxvu++NKQwlygZrm9YVbx rik3iqFxn2pv+eb1At9XAS4iiAHD7wBfrLscWss4oIX0+QhdlF5QeD+UDtTWSLRUmgKu TSLYFhP2Yov7rOaNOVnrJ1Ue9AGkbKsoV4yhOKQWWBxpoIt3Cgvtd8DPIBEaHWbnyZdY bNvwUCsYwxiiALmPWXAIthFpf7ZT1iRRYRy1MCZBG5i29GqCmkwnGHzYLuEoQ5x8OPSd 74TLn+W8uust6LI74DyQWSz+jcxfBcKqy/SQLqUNXFo95DOY6IhIrkbRiDlLYuQEr5kA cSyw== X-Gm-Message-State: ALyK8tLCffwYgEDsuqLY+nO35aCWIgpcmC20K4AQwSs4yx0mkMXObVYpqgFExOIQJOIDDoXP X-Received: by 10.98.29.81 with SMTP id d78mr890282pfd.142.1465506147296; Thu, 09 Jun 2016 14:02:27 -0700 (PDT) Received: from ketosis.mtv.corp.google.com ([172.22.65.104]) by smtp.gmail.com with ESMTPSA id tn7sm12163712pac.29.2016.06.09.14.02.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 09 Jun 2016 14:02:26 -0700 (PDT) From: dbasehore@chromium.org To: linux-kernel@vger.kernel.org Cc: dbasehore@chromium.org, linux-pm@vger.kernel.org, rjw@rjwysocki.net, pavel@ucw.cz, len.brown@intel.com, tglx@linutronix.de, gnomes@lxorguk.ukuu.org.uk, peterz@infradead.org Subject: [PATCH v4 3/5] x86, apic: Add timed freeze support Date: Thu, 9 Jun 2016 14:02:17 -0700 Message-Id: <1465506139-25981-4-git-send-email-dbasehore@chromium.org> X-Mailer: git-send-email 2.8.0.rc3.226.g39d4020 In-Reply-To: <1465506139-25981-1-git-send-email-dbasehore@chromium.org> References: <1465506139-25981-1-git-send-email-dbasehore@chromium.org> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Derek Basehore This adds support to the clock event devices created by apic to use timed freeze. The apic is able to run a timer during freeze with near izero impact on modern CPUs such as skylake. This will allow S0ix, suspend-to-idle, to be validated on Intel CPUs that support it. This is needed because bugs with power settings on the SoC can prevent S0ix entry. There is also no way to check this before idling all of the CPUs. Signed-off-by: Derek Basehore --- arch/x86/kernel/apic/apic.c | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 60078a6..f0c5f92 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -475,6 +475,26 @@ static int lapic_next_deadline(unsigned long delta, return 0; } +static bool lapic_event_expired(struct clock_event_device *evt) +{ + u32 cct; + + cct = apic_read(APIC_TMCCT); + return cct == 0; +} + +static bool lapic_deadline_expired(struct clock_event_device *evt) +{ + u64 msr; + + /* + * When the timer interrupt is triggered, the register is cleared, so a + * non-zero value indicates a pending timer event. + */ + rdmsrl(MSR_IA32_TSC_DEADLINE, msr); + return msr == 0; +} + static int lapic_timer_shutdown(struct clock_event_device *evt) { unsigned int v; @@ -529,12 +549,14 @@ static struct clock_event_device lapic_clockevent = { .name = "lapic", .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP - | CLOCK_EVT_FEAT_DUMMY, + | CLOCK_EVT_FEAT_DUMMY | + CLOCK_EVT_FEAT_FREEZE, .shift = 32, .set_state_shutdown = lapic_timer_shutdown, .set_state_periodic = lapic_timer_set_periodic, .set_state_oneshot = lapic_timer_set_oneshot, .set_next_event = lapic_next_event, + .event_expired = lapic_event_expired, .broadcast = lapic_timer_broadcast, .rating = 100, .irq = -1, @@ -562,6 +584,7 @@ static void setup_APIC_timer(void) levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_DUMMY); levt->set_next_event = lapic_next_deadline; + levt->event_expired = lapic_deadline_expired; clockevents_config_and_register(levt, (tsc_khz / TSC_DIVISOR) * 1000, 0xF, ~0UL);