From patchwork Fri Sep 2 21:08:43 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: huang lin X-Patchwork-Id: 9311651 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 01BE860865 for ; Fri, 2 Sep 2016 21:10:22 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E324029825 for ; Fri, 2 Sep 2016 21:10:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D7C972978B; Fri, 2 Sep 2016 21:10:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.9 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3820C29825 for ; Fri, 2 Sep 2016 21:10:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754574AbcIBVJv (ORCPT ); Fri, 2 Sep 2016 17:09:51 -0400 Received: from mail-pf0-f193.google.com ([209.85.192.193]:35815 "EHLO mail-pf0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754377AbcIBVIx (ORCPT ); Fri, 2 Sep 2016 17:08:53 -0400 Received: by mail-pf0-f193.google.com with SMTP id h186so6199642pfg.2; Fri, 02 Sep 2016 14:08:52 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=rG5JvHNcJU4WHv4IVqlFDShP9XcSOQ2Q5yokLUAlQxY=; b=g6OBTR7PHqutZ23cDaXT5fGtMqVslTsgMN59Q7dyzdfI5g+kcjLA2f9cmVDVcFTz9F nxkPi150jU8BVSpba+/rEe5uF/kK4A3/Ly2eFUKgQsxAgbdKb8M0adnyW2NZ4eAIpzSa p0jgkpYhkELEKhkBUO0oSZJH/Qw8QxeujYCAkcoQYswmDQA7ATesRtpLU4r0s0a6t166 wAaMVGznMn/D9VaO+pr3n+xG5jGeM+p/LRLn40F2a8cWB5mLtz0GUNddzW5+6T5xYVbD nrxuHOUNTNySvISO8H/f6npzy5Sv9mrzSb/tgdyXavNzIcsob1veS9e7oU6P+kvSQJ+R VfRg== X-Gm-Message-State: AE9vXwPOHeG5l9mcQzO3Y5CiKqg/fsb7GpoSU87FLbYu4mCCU4wkdMvLJplxAwVUn0aN3A== X-Received: by 10.98.216.199 with SMTP id e190mr39942333pfg.123.1472850532189; Fri, 02 Sep 2016 14:08:52 -0700 (PDT) Received: from hl-ThinkPad-X240.corp.google.com ([172.22.52.196]) by smtp.gmail.com with ESMTPSA id n69sm16832997pfa.77.2016.09.02.14.08.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 02 Sep 2016 14:08:51 -0700 (PDT) From: Lin Huang To: heiko@sntech.de Cc: myungjoo.ham@samsung.com, mark.yao@rock-chips.com, cw00.choi@samsung.com, airlied@linux.ie, mturquette@baylibre.com, dbasehore@chromium.org, sboyd@codeaurora.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, dianders@chromium.org, linux-rockchip@lists.infradead.org, kyungmin.park@samsung.com, linux-arm-kernel@lists.infradead.org, tixy@linaro.org, typ@rock-chips.com, sudeep.holla@arm.com, mark.rutland@arm.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, Lin Huang Subject: [PATCH v9 3/5] Documentation: bindings: add dt documentation for rk3399 dmc Date: Sat, 3 Sep 2016 05:08:43 +0800 Message-Id: <1472850525-25273-4-git-send-email-hl@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1472850525-25273-1-git-send-email-hl@rock-chips.com> References: <1472850525-25273-1-git-send-email-hl@rock-chips.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the documentation for rockchip rk3399 dmc driver. Signed-off-by: Lin Huang Reviewed-by: Chanwoo Choi --- Changes in v9: - add ddr timing property to node Changes in v8: - add ddr timing properties Changes in v7: - None Changes in v6: -Add more detail in Documentation Changes in v5: -None Changes in v4: -None Changes in v3: -None Changes in v2: -None Changes in v1: -None .../devicetree/bindings/devfreq/rk3399_dmc.txt | 202 +++++++++++++++++++++ 1 file changed, 202 insertions(+) create mode 100644 Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt new file mode 100644 index 0000000..f187c8fa --- /dev/null +++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt @@ -0,0 +1,202 @@ +* Rockchip rk3399 DMC(Dynamic Memory Controller) device + +Required properties: +- compatible: Must be "rockchip,rk3399-dmc". +- devfreq-events: Node to get DDR loading, Refer to + Documentation/devicetree/bindings/devfreq/ + rockchip-dfi.txt +- interrupts: The interrupt number to the CPU. The interrupt + specifier format depends on the interrupt controller. + It should be DCF interrupts, when DDR dvfs finish, + it will happen. +- clocks: Phandles for clock specified in "clock-names" property +- clock-names : The name of clock used by the DFI, must be + "pclk_ddr_mon"; +- operating-points-v2: Refer to Documentation/devicetree/bindings/power/opp.txt + for details. +- center-supply: DMC supply node. +- status: Marks the node enabled/disabled. + +Following properties are ddr timing: + +- dram_speed_bin : Value is defined at include/dt-bindings/clock/ddr.h, + it select ddr3 cl-trp-trcd type, default value + "DDR3_DEFAULT".it must selected according to + "Speed Bin" in ddr3 datasheet, DO NOT use smaller + "Speed Bin" than ddr3 exactly is. + +- pd_idle : Config the PD_IDLE value, defined the power-down idle + period, memories are places into power-down mode if + bus is idle for PD_IDLE DFI clocks. + +- sr_idle : Configure the SR_IDLE value, defined the selfrefresh + idle period, memories are places into self-refresh + mode if bus is idle for SR_IDLE*1024 DFI clocks + (DFI clocks freq is half of dram's clocks), defaule + value is "0". + +- sr_mc_gate_idle : Defined the self-refresh with memory and controller + clock gating idle period, memories are places into + self-refresh mode and memory controller clock arg + gating if bus is idle for sr_mc_gate_idle*1024 DFI + clocks. + +- srpd_lite_idle : Defined the self-refresh power down idle period, + memories are places into self-refresh power down + mode if bus is idle for srpd_lite_idle*1024 DFI + clocks. This parameter is for LPDDR4 only. + +- standby_idle : Defined the standby idle period, memories are places + into self-refresh than controller, pi, phy and dram + clock will gating if bus is idle for + standby_idle * DFI clocks. + +- dram_dll_disb_freq : It's defined the DDR3 dll bypass frequency in MHz + when ddr freq less than DRAM_DLL_DISB_FREQ, ddr3 + dll will bypssed note: if dll was bypassed, the + odt also stop working. + +- phy_dll_disb_freq : Defined the PHY dll bypass frequency in MHz (Mega Hz), + when ddr freq less than DRAM_DLL_DISB_FREQ, phy dll + will bypssed. note: phy dll and phy odt are + independent + +- ddr3_odt_disb_freq : When dram type is DDR3, this parameter defined the + odt disable frequency in MHz (Mega Hz), when ddr + frequency less then ddr3_odt_disb_freq, the odt + on dram side and controller side are both disabled. + +- ddr3_drv : When dram type is DDR3, this parameter define the + dram side driver stength in ohm, default value is + DDR3_DS_40ohm. + +- ddr3_odt : When dram type is DDR3, this parameter define the + dram side ODT stength in ohm, default value is + DDR3_ODT_120ohm. + +- phy_ddr3_ca_drv : When dram type is DDR3, this parameter define the phy + side CA line(incluing command line, address line and + clock line) driver strength. default value is + PHY_DRV_ODT_40. + +- phy_ddr3_dq_drv : When dram type is DDR3, this parameter define the phy + side DQ line(incluing DQS/DQ/DM line) driver strength. + default value is PHY_DRV_ODT_40. + +- phy_ddr3_odt : When dram type is DDR3, this parameter define the + phy side odt strength, default value is + PHY_DRV_ODT_240. + +- lpddr3_odt_disb_freq : When dram type is LPDDR3, this parameter defined then + odt disable frequency in MHz (Mega Hz), when ddr + frequency less then ddr3_odt_disb_freq, the odt on + dram side and controller side are both disabled. + +- lpddr3_drv : When dram type is LPDDR3, this parameter define the + dram side driver stength in ohm, default value is + LP3_DS_34ohm. + +- lpddr3_odt : When dram type is LPDDR3, this parameter define the + dram side ODT stength in ohm, default value is + LP3_ODT_240ohm. + +- phy_lpddr3_ca_drv : When dram type is LPDDR3, this parameter define the + phy side CA line(incluing command line, address line + and clock line) driver strength. default value is + PHY_DRV_ODT_40. + +- phy_lpddr3_dq_drv : When dram type is LPDDR3, this parameter define the + phy side DQ line(incluing DQS/DQ/DM line) driver + strength. default value is PHY_DRV_ODT_40. + +- phy_lpddr3_odt : When dram type is LPDDR3, this parameter define the phy + side odt strength, default value is PHY_DRV_ODT_240. + +- lpddr4_odt_disb_freq : When dram type is LPDDR4, this parameter defined the + odt disable frequency in MHz (Mega Hz), when ddr + frequency less then ddr3_odt_disb_freq, the odt on + dram side and controller side are both disabled. + +- lpddr4_drv : When dram type is LPDDR4, this parameter define the + dram side driver stength in ohm, default value is + LP4_PDDS_60ohm. + +- lpddr4_dq_odt : When dram type is LPDDR4, this parameter define the + dram side ODT on dqs/dq line stength in ohm, default + value is LP4_DQ_ODT_40ohm. + +- lpddr4_ca_odt : When dram type is LPDDR4, this parameter define the + dram side ODT on ca line stength in ohm, default value + is LP4_CA_ODT_40ohm. + +- phy_lpddr4_ca_drv : When dram type is LPDDR4, this parameter define the + phy side CA line(incluing command address line) + driver strength. default value is PHY_DRV_ODT_40. + +- phy_lpddr4_ck_cs_drv : When dram type is LPDDR4, this parameter define the + phy side clock line and cs line driver strength. + default value is PHY_DRV_ODT_80. + +- phy_lpddr4_dq_drv : When dram type is LPDDR4, this parameter define the + phy side DQ line(incluing DQS/DQ/DM line) driver + strength. default value is PHY_DRV_ODT_80. + +- phy_lpddr4_odt : When dram type is LPDDR4, this parameter define the + phy side odt strength, default value is PHY_DRV_ODT_60. + +Example: + dmc_opp_table: dmc_opp_table { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <900000>; + }; + opp01 { + opp-hz = /bits/ 64 <666000000>; + opp-microvolt = <900000>; + }; + }; + + dmc: dmc { + compatible = "rockchip,rk3399-dmc"; + devfreq-events = <&dfi>; + interrupts = ; + clocks = <&cru SCLK_DDRCLK>; + clock-names = "dmc_clk"; + operating-points-v2 = <&dmc_opp_table>; + center-supply = <&ppvar_centerlogic>; + upthreshold = <15>; + downdifferential = <10>; + rockchip,ddr3_speed_bin = <21>; + rockchip,pd_idle = <0x40>; + rockchip,sr_idle = <0x2>; + rockchip,sr_mc_gate_idle = <0x3>; + rockchip,srpd_lite_idle = <0x4>; + rockchip,standby_idle = <0x2000>; + rockchip,dram_dll_dis_freq = <300>; + rockchip,phy_dll_dis_freq = <125>; + rockchip,auto_pd_dis_freq = <666>; + rockchip,ddr3_odt_dis_freq = <333>; + rockchip,ddr3_drv = ; + rockchip,ddr3_odt = ; + rockchip,phy_ddr3_ca_drv = ; + rockchip,phy_ddr3_dq_drv = ; + rockchip,phy_ddr3_odt = ; + rockchip,lpddr3_odt_dis_freq = <333>; + rockchip,lpddr3_drv = ; + rockchip,lpddr3_odt = ; + rockchip,phy_lpddr3_ca_drv = ; + rockchip,phy_lpddr3_dq_drv = ; + rockchip,phy_lpddr3_odt = ; + rockchip,lpddr4_odt_dis_freq = <333>; + rockchip,lpddr4_drv = ; + rockchip,lpddr4_dq_odt = ; + rockchip,lpddr4_ca_odt = ; + rockchip,phy_lpddr4_ca_drv = ; + rockchip,phy_lpddr4_ck_cs_drv = ; + rockchip,phy_lpddr4_dq_drv = ; + rockchip,phy_lpddr4_odt = ; + status = "disabled"; + }; +